1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 4 * 5 * Copyright (C) 2012 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 18 #define CONFIG_X600 /* on X600 board */ 19 #define CONFIG_SYS_GENERIC_BOARD 20 21 #include <asm/arch/hardware.h> 22 23 /* Timer, HZ specific defines */ 24 #define CONFIG_SYS_HZ_CLOCK 8300000 25 26 #define CONFIG_SYS_TEXT_BASE 0x00800040 27 #define CONFIG_SYS_FLASH_BASE 0xf8000000 28 /* Reserve 8KiB for SPL */ 29 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 30 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 31 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 32 CONFIG_SYS_SPL_LEN) 33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 34 #define CONFIG_SYS_MONITOR_LEN 0x60000 35 36 #define CONFIG_ENV_IS_IN_FLASH 37 38 /* Serial Configuration (PL011) */ 39 #define CONFIG_SYS_SERIAL0 0xD0000000 40 #define CONFIG_SYS_SERIAL1 0xD0080000 41 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 42 (void *)CONFIG_SYS_SERIAL1 } 43 #define CONFIG_PL011_SERIAL 44 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 45 #define CONFIG_CONS_INDEX 0 46 #define CONFIG_BAUDRATE 115200 47 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 48 57600, 115200 } 49 #define CONFIG_SYS_LOADS_BAUD_CHANGE 50 51 /* NOR FLASH config options */ 52 #define CONFIG_ST_SMI 53 #define CONFIG_SYS_MAX_FLASH_BANKS 1 54 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 55 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 56 #define CONFIG_SYS_MAX_FLASH_SECT 128 57 #define CONFIG_SYS_FLASH_EMPTY_INFO 58 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 59 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 60 61 /* NAND FLASH config options */ 62 #define CONFIG_NAND_FSMC 63 #define CONFIG_SYS_NAND_SELF_INIT 64 #define CONFIG_SYS_MAX_NAND_DEVICE 1 65 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 66 #define CONFIG_MTD_ECC_SOFT 67 #define CONFIG_SYS_FSMC_NAND_8BIT 68 #define CONFIG_SYS_NAND_ONFI_DETECTION 69 70 /* UBI/UBI config options */ 71 #define CONFIG_MTD_DEVICE 72 #define CONFIG_MTD_PARTITIONS 73 #define CONFIG_RBTREE 74 75 /* Ethernet config options */ 76 #define CONFIG_MII 77 #define CONFIG_PHYLIB 78 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 79 #define CONFIG_PHY_ADDR 0 /* PHY address */ 80 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 81 82 #define CONFIG_SPEAR_GPIO 83 84 /* I2C config options */ 85 #define CONFIG_SYS_I2C 86 #define CONFIG_SYS_I2C_DW 87 #define CONFIG_SYS_I2C_BASE 0xD0200000 88 #define CONFIG_SYS_I2C_SPEED 400000 89 #define CONFIG_SYS_I2C_SLAVE 0x02 90 #define CONFIG_I2C_CHIPADDRESS 0x50 91 92 #define CONFIG_RTC_M41T62 1 93 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 94 95 /* FPGA config options */ 96 #define CONFIG_FPGA 97 #define CONFIG_FPGA_XILINX 98 #define CONFIG_FPGA_SPARTAN3 99 #define CONFIG_FPGA_COUNT 1 100 101 /* 102 * Command support defines 103 */ 104 #define CONFIG_CMD_CACHE 105 #define CONFIG_CMD_DATE 106 #define CONFIG_CMD_DHCP 107 #define CONFIG_CMD_ENV 108 #define CONFIG_CMD_FPGA 109 #define CONFIG_CMD_FPGA_LOADMK 110 #define CONFIG_CMD_GPIO 111 #define CONFIG_CMD_I2C 112 #define CONFIG_CMD_MEMORY 113 #define CONFIG_CMD_MII 114 #define CONFIG_CMD_MTDPARTS 115 #define CONFIG_CMD_NAND 116 #define CONFIG_CMD_PING 117 #define CONFIG_CMD_RUN 118 #define CONFIG_CMD_SAVES 119 #define CONFIG_CMD_UBI 120 #define CONFIG_CMD_UBIFS 121 #define CONFIG_LZO 122 123 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 124 #include <config_cmd_default.h> 125 126 #define CONFIG_BOOTDELAY 3 127 128 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 129 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 130 131 /* 132 * U-Boot Environment placing definitions. 133 */ 134 #define CONFIG_ENV_SECT_SIZE 0x00010000 135 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 136 CONFIG_SYS_MONITOR_LEN) 137 #define CONFIG_ENV_SIZE 0x02000 138 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 139 CONFIG_ENV_SECT_SIZE) 140 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 141 142 /* Miscellaneous configurable options */ 143 #define CONFIG_ARCH_CPU_INIT 144 #define CONFIG_DISPLAY_CPUINFO 145 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 146 #define CONFIG_CMDLINE_TAG 147 #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ 148 #define CONFIG_SETUP_MEMORY_TAGS 149 #define CONFIG_MISC_INIT_R 150 #define CONFIG_BOARD_LATE_INIT 151 #define CONFIG_LOOPW /* enable loopw command */ 152 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 153 #define CONFIG_ZERO_BOOTDELAY_CHECK 154 #define CONFIG_AUTOBOOT_KEYED 155 #define CONFIG_AUTOBOOT_STOP_STR " " 156 #define CONFIG_AUTOBOOT_PROMPT \ 157 "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay 158 159 #define CONFIG_SYS_MEMTEST_START 0x00800000 160 #define CONFIG_SYS_MEMTEST_END 0x04000000 161 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 162 #define CONFIG_IDENT_STRING "-SPEAr" 163 #define CONFIG_SYS_LONGHELP 164 #define CONFIG_SYS_PROMPT "X600> " 165 #define CONFIG_CMDLINE_EDITING 166 #define CONFIG_SYS_CBSIZE 256 167 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 168 sizeof(CONFIG_SYS_PROMPT) + 16) 169 #define CONFIG_SYS_MAXARGS 16 170 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 171 #define CONFIG_SYS_LOAD_ADDR 0x00800000 172 #define CONFIG_SYS_CONSOLE_INFO_QUIET 173 174 /* Use last 2 lwords in internal SRAM for bootcounter */ 175 #define CONFIG_BOOTCOUNT_LIMIT 176 #define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8 177 178 #define CONFIG_HOSTNAME x600 179 #define CONFIG_UBI_PART ubi0 180 #define CONFIG_UBIFS_VOLUME rootfs 181 182 #define MTDIDS_DEFAULT "nand0=nand" 183 #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" 184 185 #define CONFIG_EXTRA_ENV_SETTINGS \ 186 "u-boot_addr=1000000\0" \ 187 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ 188 "load=tftp ${u-boot_addr} ${u-boot}\0" \ 189 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 190 " +${filesize};" \ 191 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 192 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ 193 " ${filesize};" \ 194 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 195 " +${filesize}\0" \ 196 "upd=run load update\0" \ 197 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ 198 "part=" __stringify(CONFIG_UBI_PART) "\0" \ 199 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ 200 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 201 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 202 " ${filesize}\0" \ 203 "upd_ubifs=run load_ubifs update_ubifs\0" \ 204 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 205 "ubi create ${vol} 4000000\0" \ 206 "netdev=eth0\0" \ 207 "rootpath=/opt/eldk-4.2/arm\0" \ 208 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 209 "nfsroot=${serverip}:${rootpath}\0" \ 210 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 211 "boot_part=0\0" \ 212 "altbootcmd=if test $boot_part -eq 0;then " \ 213 "echo Switching to partition 1!;" \ 214 "setenv boot_part 1;" \ 215 "else; " \ 216 "echo Switching to partition 0!;" \ 217 "setenv boot_part 0;" \ 218 "fi;" \ 219 "saveenv;boot\0" \ 220 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 221 "root=ubi0:rootfs rootfstype=ubifs\0" \ 222 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 223 "kernel_fs=/boot/uImage \0" \ 224 "kernel_addr=1000000\0" \ 225 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ 226 __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 227 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 228 "dtb_addr=1800000\0" \ 229 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 230 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 231 "addip=setenv bootargs ${bootargs} " \ 232 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 233 ":${hostname}:${netdev}:off panic=1\0" \ 234 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 235 "${baudrate}\0" \ 236 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 237 "net_nfs=run load_dtb load_kernel; " \ 238 "run nfsargs addip addcon addmtd addmisc;" \ 239 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 240 "mtdids=" MTDIDS_DEFAULT "\0" \ 241 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 242 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 243 " addcon addmisc addmtd;" \ 244 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 245 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ 246 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 247 "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 248 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 249 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 250 "bootcmd=run nand_ubifs\0" \ 251 "\0" 252 253 /* Stack sizes */ 254 #define CONFIG_STACKSIZE (512 * 1024) 255 256 /* Physical Memory Map */ 257 #define CONFIG_NR_DRAM_BANKS 1 258 #define PHYS_SDRAM_1 0x00000000 259 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 260 261 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 262 #define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 263 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 264 265 #define CONFIG_SYS_INIT_SP_OFFSET \ 266 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 267 268 #define CONFIG_SYS_INIT_SP_ADDR \ 269 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 270 271 /* 272 * SPL related defines 273 */ 274 #define CONFIG_SPL_TEXT_BASE 0xd2800b00 275 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 276 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" 277 278 #define CONFIG_SPL_SERIAL_SUPPORT 279 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ 280 #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ 281 #define CONFIG_SPL_NO_PRINTF 282 283 /* 284 * Please select/define only one of the following 285 * Each definition corresponds to a supported DDR chip. 286 * DDR configuration is based on the following selection 287 */ 288 #define CONFIG_DDR_MT47H64M16 1 289 #define CONFIG_DDR_MT47H32M16 0 290 #define CONFIG_DDR_MT47H128M8 0 291 292 /* 293 * Synchronous/Asynchronous operation of DDR 294 * 295 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 296 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 297 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 298 */ 299 #define CONFIG_DDR_2HCLK 1 300 #define CONFIG_DDR_HCLK 0 301 #define CONFIG_DDR_PLL2 0 302 303 /* 304 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 305 * or not. Modify/Add to only these macros to define new boot types 306 */ 307 #define USB_BOOT_SUPPORTED 0 308 #define PCIE_BOOT_SUPPORTED 0 309 #define SNOR_BOOT_SUPPORTED 1 310 #define NAND_BOOT_SUPPORTED 1 311 #define PNOR_BOOT_SUPPORTED 0 312 #define TFTP_BOOT_SUPPORTED 0 313 #define UART_BOOT_SUPPORTED 0 314 #define SPI_BOOT_SUPPORTED 0 315 #define I2C_BOOT_SUPPORTED 0 316 #define MMC_BOOT_SUPPORTED 0 317 318 #endif /* __CONFIG_H */ 319