1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 4 * 5 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 18 #define CONFIG_X600 /* on X600 board */ 19 20 #include <asm/arch/hardware.h> 21 22 /* Timer, HZ specific defines */ 23 #define CONFIG_SYS_HZ_CLOCK 8300000 24 25 #define CONFIG_SYS_TEXT_BASE 0x00800040 26 #define CONFIG_SYS_FLASH_BASE 0xf8000000 27 /* Reserve 8KiB for SPL */ 28 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 29 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 30 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 31 CONFIG_SYS_SPL_LEN) 32 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 34 #define CONFIG_SYS_MONITOR_LEN 0x60000 35 36 /* Serial Configuration (PL011) */ 37 #define CONFIG_SYS_SERIAL0 0xD0000000 38 #define CONFIG_SYS_SERIAL1 0xD0080000 39 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 40 (void *)CONFIG_SYS_SERIAL1 } 41 #define CONFIG_PL011_SERIAL 42 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 43 #define CONFIG_CONS_INDEX 0 44 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 45 57600, 115200 } 46 #define CONFIG_SYS_LOADS_BAUD_CHANGE 47 48 /* NOR FLASH config options */ 49 #define CONFIG_ST_SMI 50 #define CONFIG_SYS_MAX_FLASH_BANKS 1 51 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 52 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 53 #define CONFIG_SYS_MAX_FLASH_SECT 128 54 #define CONFIG_SYS_FLASH_EMPTY_INFO 55 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 56 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 57 58 /* NAND FLASH config options */ 59 #define CONFIG_NAND_FSMC 60 #define CONFIG_SYS_NAND_SELF_INIT 61 #define CONFIG_SYS_MAX_NAND_DEVICE 1 62 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 63 #define CONFIG_MTD_ECC_SOFT 64 #define CONFIG_SYS_FSMC_NAND_8BIT 65 #define CONFIG_SYS_NAND_ONFI_DETECTION 66 #define CONFIG_NAND_ECC_BCH 67 #define CONFIG_BCH 68 69 /* UBI/UBI config options */ 70 #define CONFIG_MTD_DEVICE 71 #define CONFIG_MTD_PARTITIONS 72 73 /* Ethernet config options */ 74 #define CONFIG_MII 75 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 76 #define CONFIG_PHY_ADDR 0 /* PHY address */ 77 78 #define CONFIG_SPEAR_GPIO 79 80 /* I2C config options */ 81 #define CONFIG_SYS_I2C 82 #define CONFIG_SYS_I2C_BASE 0xD0200000 83 #define CONFIG_SYS_I2C_SPEED 400000 84 #define CONFIG_SYS_I2C_SLAVE 0x02 85 #define CONFIG_I2C_CHIPADDRESS 0x50 86 87 #define CONFIG_RTC_M41T62 1 88 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 89 90 /* FPGA config options */ 91 #define CONFIG_FPGA 92 #define CONFIG_FPGA_XILINX 93 #define CONFIG_FPGA_SPARTAN3 94 #define CONFIG_FPGA_COUNT 1 95 96 /* USB EHCI options */ 97 #define CONFIG_USB_EHCI_SPEAR 98 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 99 100 /* Filesystem support (for USB key) */ 101 #define CONFIG_SUPPORT_VFAT 102 103 104 /* 105 * U-Boot Environment placing definitions. 106 */ 107 #define CONFIG_ENV_SECT_SIZE 0x00010000 108 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 109 CONFIG_SYS_MONITOR_LEN) 110 #define CONFIG_ENV_SIZE 0x02000 111 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 112 CONFIG_ENV_SECT_SIZE) 113 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 114 115 /* Miscellaneous configurable options */ 116 #define CONFIG_ARCH_CPU_INIT 117 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 118 #define CONFIG_CMDLINE_TAG 119 #define CONFIG_SETUP_MEMORY_TAGS 120 #define CONFIG_MISC_INIT_R 121 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 122 123 #define CONFIG_SYS_MEMTEST_START 0x00800000 124 #define CONFIG_SYS_MEMTEST_END 0x04000000 125 #define CONFIG_SYS_MALLOC_LEN (8 << 20) 126 #define CONFIG_SYS_LONGHELP 127 #define CONFIG_CMDLINE_EDITING 128 #define CONFIG_AUTO_COMPLETE 129 #define CONFIG_SYS_CBSIZE 256 130 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 131 sizeof(CONFIG_SYS_PROMPT) + 16) 132 #define CONFIG_SYS_MAXARGS 16 133 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 134 #define CONFIG_SYS_LOAD_ADDR 0x00800000 135 136 /* Use last 2 lwords in internal SRAM for bootcounter */ 137 #define CONFIG_BOOTCOUNT_LIMIT 138 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \ 139 CONFIG_SRAM_SIZE) 140 141 #define CONFIG_HOSTNAME x600 142 #define CONFIG_UBI_PART ubi0 143 #define CONFIG_UBIFS_VOLUME rootfs 144 145 #define MTDIDS_DEFAULT "nand0=nand" 146 #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" 147 148 #define CONFIG_EXTRA_ENV_SETTINGS \ 149 "u-boot_addr=1000000\0" \ 150 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ 151 "load=tftp ${u-boot_addr} ${u-boot}\0" \ 152 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 153 " +${filesize};" \ 154 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 155 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ 156 " ${filesize};" \ 157 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 158 " +${filesize}\0" \ 159 "upd=run load update\0" \ 160 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ 161 "part=" __stringify(CONFIG_UBI_PART) "\0" \ 162 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ 163 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 164 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 165 " ${filesize}\0" \ 166 "upd_ubifs=run load_ubifs update_ubifs\0" \ 167 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 168 "ubi create ${vol} 4000000\0" \ 169 "netdev=eth0\0" \ 170 "rootpath=/opt/eldk-4.2/arm\0" \ 171 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 172 "nfsroot=${serverip}:${rootpath}\0" \ 173 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 174 "boot_part=0\0" \ 175 "altbootcmd=if test $boot_part -eq 0;then " \ 176 "echo Switching to partition 1!;" \ 177 "setenv boot_part 1;" \ 178 "else; " \ 179 "echo Switching to partition 0!;" \ 180 "setenv boot_part 0;" \ 181 "fi;" \ 182 "saveenv;boot\0" \ 183 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 184 "root=ubi0:rootfs rootfstype=ubifs\0" \ 185 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 186 "kernel_fs=/boot/uImage \0" \ 187 "kernel_addr=1000000\0" \ 188 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ 189 __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 190 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 191 "dtb_addr=1800000\0" \ 192 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 193 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 194 "addip=setenv bootargs ${bootargs} " \ 195 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 196 ":${hostname}:${netdev}:off panic=1\0" \ 197 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 198 "${baudrate}\0" \ 199 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 200 "net_nfs=run load_dtb load_kernel; " \ 201 "run nfsargs addip addcon addmtd addmisc;" \ 202 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 203 "mtdids=" MTDIDS_DEFAULT "\0" \ 204 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 205 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 206 " addcon addmisc addmtd;" \ 207 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 208 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ 209 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 210 "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 211 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 212 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 213 "bootcmd=run nand_ubifs\0" \ 214 "\0" 215 216 /* Physical Memory Map */ 217 #define CONFIG_NR_DRAM_BANKS 1 218 #define PHYS_SDRAM_1 0x00000000 219 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 220 221 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 222 #define CONFIG_SRAM_BASE 0xd2800000 223 /* Preserve the last 2 lwords for the boot-counter */ 224 #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) 225 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE 226 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE 227 228 #define CONFIG_SYS_INIT_SP_OFFSET \ 229 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 230 231 #define CONFIG_SYS_INIT_SP_ADDR \ 232 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 233 234 /* 235 * SPL related defines 236 */ 237 #define CONFIG_SPL_TEXT_BASE 0xd2800b00 238 #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) 239 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 240 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" 241 242 #define CONFIG_SPL_FRAMEWORK 243 244 /* 245 * Please select/define only one of the following 246 * Each definition corresponds to a supported DDR chip. 247 * DDR configuration is based on the following selection 248 */ 249 #define CONFIG_DDR_MT47H64M16 1 250 #define CONFIG_DDR_MT47H32M16 0 251 #define CONFIG_DDR_MT47H128M8 0 252 253 /* 254 * Synchronous/Asynchronous operation of DDR 255 * 256 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 257 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 258 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 259 */ 260 #define CONFIG_DDR_2HCLK 1 261 #define CONFIG_DDR_HCLK 0 262 #define CONFIG_DDR_PLL2 0 263 264 /* 265 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 266 * or not. Modify/Add to only these macros to define new boot types 267 */ 268 #define USB_BOOT_SUPPORTED 0 269 #define PCIE_BOOT_SUPPORTED 0 270 #define SNOR_BOOT_SUPPORTED 1 271 #define NAND_BOOT_SUPPORTED 1 272 #define PNOR_BOOT_SUPPORTED 0 273 #define TFTP_BOOT_SUPPORTED 0 274 #define UART_BOOT_SUPPORTED 0 275 #define SPI_BOOT_SUPPORTED 0 276 #define I2C_BOOT_SUPPORTED 0 277 #define MMC_BOOT_SUPPORTED 0 278 279 #endif /* __CONFIG_H */ 280