1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 4 * 5 * Copyright (C) 2012 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 18 #define CONFIG_X600 /* on X600 board */ 19 20 #include <asm/arch/hardware.h> 21 22 /* Timer, HZ specific defines */ 23 #define CONFIG_SYS_HZ_CLOCK 8300000 24 25 #define CONFIG_SYS_TEXT_BASE 0x00800040 26 #define CONFIG_SYS_FLASH_BASE 0xf8000000 27 /* Reserve 8KiB for SPL */ 28 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 29 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 30 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 31 CONFIG_SYS_SPL_LEN) 32 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 33 #define CONFIG_SYS_MONITOR_LEN 0x60000 34 35 #define CONFIG_ENV_IS_IN_FLASH 36 37 /* Serial Configuration (PL011) */ 38 #define CONFIG_SYS_SERIAL0 0xD0000000 39 #define CONFIG_SYS_SERIAL1 0xD0080000 40 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 41 (void *)CONFIG_SYS_SERIAL1 } 42 #define CONFIG_PL011_SERIAL 43 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 44 #define CONFIG_CONS_INDEX 0 45 #define CONFIG_BAUDRATE 115200 46 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 47 57600, 115200 } 48 #define CONFIG_SYS_LOADS_BAUD_CHANGE 49 50 /* NOR FLASH config options */ 51 #define CONFIG_ST_SMI 52 #define CONFIG_SYS_MAX_FLASH_BANKS 1 53 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 54 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 55 #define CONFIG_SYS_MAX_FLASH_SECT 128 56 #define CONFIG_SYS_FLASH_EMPTY_INFO 57 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 58 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 59 60 /* NAND FLASH config options */ 61 #define CONFIG_NAND_FSMC 62 #define CONFIG_SYS_NAND_SELF_INIT 63 #define CONFIG_SYS_MAX_NAND_DEVICE 1 64 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 65 #define CONFIG_MTD_ECC_SOFT 66 #define CONFIG_SYS_FSMC_NAND_8BIT 67 #define CONFIG_SYS_NAND_ONFI_DETECTION 68 69 /* UBI/UBI config options */ 70 #define CONFIG_MTD_DEVICE 71 #define CONFIG_MTD_PARTITIONS 72 #define CONFIG_RBTREE 73 74 /* Ethernet config options */ 75 #define CONFIG_MII 76 #define CONFIG_DESIGNWARE_ETH 77 #define CONFIG_NET_MULTI 78 #define CONFIG_PHYLIB 79 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 80 #define CONFIG_PHY_ADDR 0 /* PHY address */ 81 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 82 83 #define CONFIG_SPEAR_GPIO 84 85 /* I2C config options */ 86 #define CONFIG_HARD_I2C 87 #define CONFIG_DW_I2C 88 #define CONFIG_SYS_I2C_BASE 0xD0200000 89 #define CONFIG_SYS_I2C_SPEED 400000 90 #define CONFIG_SYS_I2C_SLAVE 0x02 91 #define CONFIG_I2C_CHIPADDRESS 0x50 92 93 #define CONFIG_RTC_M41T62 1 94 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 95 96 /* FPGA config options */ 97 #define CONFIG_FPGA 98 #define CONFIG_FPGA_XILINX 99 #define CONFIG_FPGA_SPARTAN3 100 #define CONFIG_FPGA_COUNT 1 101 102 /* 103 * Command support defines 104 */ 105 #define CONFIG_CMD_CACHE 106 #define CONFIG_CMD_DATE 107 #define CONFIG_CMD_DHCP 108 #define CONFIG_CMD_ENV 109 #define CONFIG_CMD_FPGA 110 #define CONFIG_CMD_FPGA_LOADMK 111 #define CONFIG_CMD_GPIO 112 #define CONFIG_CMD_I2C 113 #define CONFIG_CMD_MEMORY 114 #define CONFIG_CMD_MII 115 #define CONFIG_CMD_MTDPARTS 116 #define CONFIG_CMD_NAND 117 #define CONFIG_CMD_NET 118 #define CONFIG_CMD_PING 119 #define CONFIG_CMD_RUN 120 #define CONFIG_CMD_SAVES 121 #define CONFIG_CMD_UBI 122 #define CONFIG_CMD_UBIFS 123 #define CONFIG_LZO 124 125 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 126 #include <config_cmd_default.h> 127 128 #define CONFIG_BOOTDELAY 3 129 130 #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 131 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 132 133 /* 134 * U-Boot Environment placing definitions. 135 */ 136 #define CONFIG_ENV_SECT_SIZE 0x00010000 137 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 138 CONFIG_SYS_MONITOR_LEN) 139 #define CONFIG_ENV_SIZE 0x02000 140 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 141 CONFIG_ENV_SECT_SIZE) 142 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 143 144 /* Miscellaneous configurable options */ 145 #define CONFIG_ARCH_CPU_INIT 146 #define CONFIG_DISPLAY_CPUINFO 147 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 148 #define CONFIG_CMDLINE_TAG 149 #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ 150 #define CONFIG_SETUP_MEMORY_TAGS 151 #define CONFIG_MISC_INIT_R 152 #define CONFIG_BOARD_LATE_INIT 153 #define CONFIG_LOOPW /* enable loopw command */ 154 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 155 #define CONFIG_ZERO_BOOTDELAY_CHECK 156 #define CONFIG_AUTOBOOT_KEYED 157 #define CONFIG_AUTOBOOT_STOP_STR " " 158 #define CONFIG_AUTOBOOT_PROMPT \ 159 "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay 160 161 #define CONFIG_SYS_MEMTEST_START 0x00800000 162 #define CONFIG_SYS_MEMTEST_END 0x04000000 163 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 164 #define CONFIG_IDENT_STRING "-SPEAr" 165 #define CONFIG_SYS_LONGHELP 166 #define CONFIG_SYS_PROMPT "X600> " 167 #define CONFIG_CMDLINE_EDITING 168 #define CONFIG_SYS_CBSIZE 256 169 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 170 sizeof(CONFIG_SYS_PROMPT) + 16) 171 #define CONFIG_SYS_MAXARGS 16 172 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 173 #define CONFIG_SYS_LOAD_ADDR 0x00800000 174 #define CONFIG_SYS_CONSOLE_INFO_QUIET 175 176 /* Use last 2 lwords in internal SRAM for bootcounter */ 177 #define CONFIG_BOOTCOUNT_LIMIT 178 #define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8 179 180 #define CONFIG_HOSTNAME x600 181 #define CONFIG_UBI_PART ubi0 182 #define CONFIG_UBIFS_VOLUME rootfs 183 184 #define xstr(s) str(s) 185 #define str(s) #s 186 187 #define MTDIDS_DEFAULT "nand0=nand" 188 #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" 189 190 #define CONFIG_EXTRA_ENV_SETTINGS \ 191 "u-boot_addr=1000000\0" \ 192 "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \ 193 "load=tftp ${u-boot_addr} ${u-boot}\0" \ 194 "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\ 195 "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 196 "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \ 197 " ${filesize};" \ 198 "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \ 199 " +${filesize}\0" \ 200 "upd=run load update\0" \ 201 "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \ 202 "part=" xstr(CONFIG_UBI_PART) "\0" \ 203 "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \ 204 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 205 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 206 " ${filesize}\0" \ 207 "upd_ubifs=run load_ubifs update_ubifs\0" \ 208 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 209 "ubi create ${vol} 4000000\0" \ 210 "netdev=eth0\0" \ 211 "rootpath=/opt/eldk-4.2/arm\0" \ 212 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 213 "nfsroot=${serverip}:${rootpath}\0" \ 214 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 215 "boot_part=0\0" \ 216 "altbootcmd=if test $boot_part -eq 0;then " \ 217 "echo Switching to partition 1!;" \ 218 "setenv boot_part 1;" \ 219 "else; " \ 220 "echo Switching to partition 0!;" \ 221 "setenv boot_part 0;" \ 222 "fi;" \ 223 "saveenv;boot\0" \ 224 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 225 "root=ubi0:rootfs rootfstype=ubifs\0" \ 226 "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ 227 "kernel_fs=/boot/uImage \0" \ 228 "kernel_addr=1000000\0" \ 229 "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ 230 "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ 231 "dtb_addr=1800000\0" \ 232 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 233 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 234 "addip=setenv bootargs ${bootargs} " \ 235 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 236 ":${hostname}:${netdev}:off panic=1\0" \ 237 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 238 "${baudrate}\0" \ 239 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 240 "net_nfs=run load_dtb load_kernel; " \ 241 "run nfsargs addip addcon addmtd addmisc;" \ 242 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 243 "mtdids=" MTDIDS_DEFAULT "\0" \ 244 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 245 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 246 " addcon addmisc addmtd;" \ 247 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 248 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ 249 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 250 "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 251 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 252 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 253 "bootcmd=run nand_ubifs\0" \ 254 "\0" 255 256 /* Stack sizes */ 257 #define CONFIG_STACKSIZE (512 * 1024) 258 259 /* Physical Memory Map */ 260 #define CONFIG_NR_DRAM_BANKS 1 261 #define PHYS_SDRAM_1 0x00000000 262 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 263 264 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 265 #define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 266 #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 267 268 #define CONFIG_SYS_INIT_SP_OFFSET \ 269 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 270 271 #define CONFIG_SYS_INIT_SP_ADDR \ 272 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 273 274 /* 275 * SPL related defines 276 */ 277 #define CONFIG_SPL 278 #define CONFIG_SPL_TEXT_BASE 0xd2800b00 279 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 280 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" 281 282 #define CONFIG_SPL_SERIAL_SUPPORT 283 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ 284 #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ 285 #define CONFIG_SPL_NO_PRINTF 286 287 /* 288 * Please select/define only one of the following 289 * Each definition corresponds to a supported DDR chip. 290 * DDR configuration is based on the following selection 291 */ 292 #define CONFIG_DDR_MT47H64M16 1 293 #define CONFIG_DDR_MT47H32M16 0 294 #define CONFIG_DDR_MT47H128M8 0 295 296 /* 297 * Synchronous/Asynchronous operation of DDR 298 * 299 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 300 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 301 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 302 */ 303 #define CONFIG_DDR_2HCLK 1 304 #define CONFIG_DDR_HCLK 0 305 #define CONFIG_DDR_PLL2 0 306 307 /* 308 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 309 * or not. Modify/Add to only these macros to define new boot types 310 */ 311 #define USB_BOOT_SUPPORTED 0 312 #define PCIE_BOOT_SUPPORTED 0 313 #define SNOR_BOOT_SUPPORTED 1 314 #define NAND_BOOT_SUPPORTED 1 315 #define PNOR_BOOT_SUPPORTED 0 316 #define TFTP_BOOT_SUPPORTED 0 317 #define UART_BOOT_SUPPORTED 0 318 #define SPI_BOOT_SUPPORTED 0 319 #define I2C_BOOT_SUPPORTED 0 320 #define MMC_BOOT_SUPPORTED 0 321 322 #endif /* __CONFIG_H */ 323