1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 4 * 5 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 18 #define CONFIG_X600 /* on X600 board */ 19 20 #include <asm/arch/hardware.h> 21 22 /* Timer, HZ specific defines */ 23 #define CONFIG_SYS_HZ_CLOCK 8300000 24 25 #define CONFIG_SYS_TEXT_BASE 0x00800040 26 #define CONFIG_SYS_FLASH_BASE 0xf8000000 27 /* Reserve 8KiB for SPL */ 28 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 29 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 30 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 31 CONFIG_SYS_SPL_LEN) 32 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 34 #define CONFIG_SYS_MONITOR_LEN 0x60000 35 36 #define CONFIG_ENV_IS_IN_FLASH 37 38 /* Serial Configuration (PL011) */ 39 #define CONFIG_SYS_SERIAL0 0xD0000000 40 #define CONFIG_SYS_SERIAL1 0xD0080000 41 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 42 (void *)CONFIG_SYS_SERIAL1 } 43 #define CONFIG_PL011_SERIAL 44 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 45 #define CONFIG_CONS_INDEX 0 46 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 47 57600, 115200 } 48 #define CONFIG_SYS_LOADS_BAUD_CHANGE 49 50 /* NOR FLASH config options */ 51 #define CONFIG_ST_SMI 52 #define CONFIG_SYS_MAX_FLASH_BANKS 1 53 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 54 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 55 #define CONFIG_SYS_MAX_FLASH_SECT 128 56 #define CONFIG_SYS_FLASH_EMPTY_INFO 57 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 58 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 59 60 /* NAND FLASH config options */ 61 #define CONFIG_NAND_FSMC 62 #define CONFIG_SYS_NAND_SELF_INIT 63 #define CONFIG_SYS_MAX_NAND_DEVICE 1 64 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 65 #define CONFIG_MTD_ECC_SOFT 66 #define CONFIG_SYS_FSMC_NAND_8BIT 67 #define CONFIG_SYS_NAND_ONFI_DETECTION 68 #define CONFIG_NAND_ECC_BCH 69 #define CONFIG_BCH 70 71 /* UBI/UBI config options */ 72 #define CONFIG_MTD_DEVICE 73 #define CONFIG_MTD_PARTITIONS 74 #define CONFIG_RBTREE 75 76 /* Ethernet config options */ 77 #define CONFIG_MII 78 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 79 #define CONFIG_PHY_ADDR 0 /* PHY address */ 80 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 81 #define CONFIG_PHY_MICREL 82 #define CONFIG_PHY_MICREL_KSZ9031 83 84 #define CONFIG_SPEAR_GPIO 85 86 /* I2C config options */ 87 #define CONFIG_SYS_I2C 88 #define CONFIG_SYS_I2C_BASE 0xD0200000 89 #define CONFIG_SYS_I2C_SPEED 400000 90 #define CONFIG_SYS_I2C_SLAVE 0x02 91 #define CONFIG_I2C_CHIPADDRESS 0x50 92 93 #define CONFIG_RTC_M41T62 1 94 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 95 96 /* FPGA config options */ 97 #define CONFIG_FPGA 98 #define CONFIG_FPGA_XILINX 99 #define CONFIG_FPGA_SPARTAN3 100 #define CONFIG_FPGA_COUNT 1 101 102 /* USB EHCI options */ 103 #define CONFIG_USB_EHCI_SPEAR 104 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 105 106 /* 107 * Command support defines 108 */ 109 #define CONFIG_CMD_ENV 110 #define CONFIG_CMD_FPGA_LOADMK 111 #define CONFIG_CMD_MTDPARTS 112 #define CONFIG_CMD_NAND 113 #define CONFIG_CMD_SAVES 114 #define CONFIG_CMD_UBIFS 115 #define CONFIG_LZO 116 117 /* Filesystem support (for USB key) */ 118 #define CONFIG_SUPPORT_VFAT 119 120 121 /* 122 * U-Boot Environment placing definitions. 123 */ 124 #define CONFIG_ENV_SECT_SIZE 0x00010000 125 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 126 CONFIG_SYS_MONITOR_LEN) 127 #define CONFIG_ENV_SIZE 0x02000 128 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 129 CONFIG_ENV_SECT_SIZE) 130 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 131 132 /* Miscellaneous configurable options */ 133 #define CONFIG_ARCH_CPU_INIT 134 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 135 #define CONFIG_CMDLINE_TAG 136 #define CONFIG_SETUP_MEMORY_TAGS 137 #define CONFIG_MISC_INIT_R 138 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 139 140 #define CONFIG_SYS_MEMTEST_START 0x00800000 141 #define CONFIG_SYS_MEMTEST_END 0x04000000 142 #define CONFIG_SYS_MALLOC_LEN (8 << 20) 143 #define CONFIG_SYS_LONGHELP 144 #define CONFIG_CMDLINE_EDITING 145 #define CONFIG_AUTO_COMPLETE 146 #define CONFIG_SYS_CBSIZE 256 147 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 148 sizeof(CONFIG_SYS_PROMPT) + 16) 149 #define CONFIG_SYS_MAXARGS 16 150 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 151 #define CONFIG_SYS_LOAD_ADDR 0x00800000 152 153 /* Use last 2 lwords in internal SRAM for bootcounter */ 154 #define CONFIG_BOOTCOUNT_LIMIT 155 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \ 156 CONFIG_SRAM_SIZE) 157 158 #define CONFIG_HOSTNAME x600 159 #define CONFIG_UBI_PART ubi0 160 #define CONFIG_UBIFS_VOLUME rootfs 161 162 #define MTDIDS_DEFAULT "nand0=nand" 163 #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" 164 165 #define CONFIG_EXTRA_ENV_SETTINGS \ 166 "u-boot_addr=1000000\0" \ 167 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \ 168 "load=tftp ${u-boot_addr} ${u-boot}\0" \ 169 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 170 " +${filesize};" \ 171 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 172 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ 173 " ${filesize};" \ 174 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ 175 " +${filesize}\0" \ 176 "upd=run load update\0" \ 177 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \ 178 "part=" __stringify(CONFIG_UBI_PART) "\0" \ 179 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ 180 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 181 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 182 " ${filesize}\0" \ 183 "upd_ubifs=run load_ubifs update_ubifs\0" \ 184 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 185 "ubi create ${vol} 4000000\0" \ 186 "netdev=eth0\0" \ 187 "rootpath=/opt/eldk-4.2/arm\0" \ 188 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 189 "nfsroot=${serverip}:${rootpath}\0" \ 190 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 191 "boot_part=0\0" \ 192 "altbootcmd=if test $boot_part -eq 0;then " \ 193 "echo Switching to partition 1!;" \ 194 "setenv boot_part 1;" \ 195 "else; " \ 196 "echo Switching to partition 0!;" \ 197 "setenv boot_part 0;" \ 198 "fi;" \ 199 "saveenv;boot\0" \ 200 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 201 "root=ubi0:rootfs rootfstype=ubifs\0" \ 202 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 203 "kernel_fs=/boot/uImage \0" \ 204 "kernel_addr=1000000\0" \ 205 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \ 206 __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 207 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \ 208 "dtb_addr=1800000\0" \ 209 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 210 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 211 "addip=setenv bootargs ${bootargs} " \ 212 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 213 ":${hostname}:${netdev}:off panic=1\0" \ 214 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 215 "${baudrate}\0" \ 216 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 217 "net_nfs=run load_dtb load_kernel; " \ 218 "run nfsargs addip addcon addmtd addmisc;" \ 219 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 220 "mtdids=" MTDIDS_DEFAULT "\0" \ 221 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 222 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 223 " addcon addmisc addmtd;" \ 224 "bootm ${kernel_addr} - ${dtb_addr}\0" \ 225 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ 226 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 227 "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 228 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 229 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 230 "bootcmd=run nand_ubifs\0" \ 231 "\0" 232 233 /* Physical Memory Map */ 234 #define CONFIG_NR_DRAM_BANKS 1 235 #define PHYS_SDRAM_1 0x00000000 236 #define PHYS_SDRAM_1_MAXSIZE 0x40000000 237 238 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 239 #define CONFIG_SRAM_BASE 0xd2800000 240 /* Preserve the last 2 lwords for the boot-counter */ 241 #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) 242 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE 243 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE 244 245 #define CONFIG_SYS_INIT_SP_OFFSET \ 246 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 247 248 #define CONFIG_SYS_INIT_SP_ADDR \ 249 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 250 251 /* 252 * SPL related defines 253 */ 254 #define CONFIG_SPL_TEXT_BASE 0xd2800b00 255 #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) 256 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 257 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" 258 259 #define CONFIG_SPL_FRAMEWORK 260 261 /* 262 * Please select/define only one of the following 263 * Each definition corresponds to a supported DDR chip. 264 * DDR configuration is based on the following selection 265 */ 266 #define CONFIG_DDR_MT47H64M16 1 267 #define CONFIG_DDR_MT47H32M16 0 268 #define CONFIG_DDR_MT47H128M8 0 269 270 /* 271 * Synchronous/Asynchronous operation of DDR 272 * 273 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 274 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 275 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 276 */ 277 #define CONFIG_DDR_2HCLK 1 278 #define CONFIG_DDR_HCLK 0 279 #define CONFIG_DDR_PLL2 0 280 281 /* 282 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 283 * or not. Modify/Add to only these macros to define new boot types 284 */ 285 #define USB_BOOT_SUPPORTED 0 286 #define PCIE_BOOT_SUPPORTED 0 287 #define SNOR_BOOT_SUPPORTED 1 288 #define NAND_BOOT_SUPPORTED 1 289 #define PNOR_BOOT_SUPPORTED 0 290 #define TFTP_BOOT_SUPPORTED 0 291 #define UART_BOOT_SUPPORTED 0 292 #define SPI_BOOT_SUPPORTED 0 293 #define I2C_BOOT_SUPPORTED 0 294 #define MMC_BOOT_SUPPORTED 0 295 296 #endif /* __CONFIG_H */ 297