xref: /openbmc/u-boot/include/configs/x600.h (revision 03bf9d58)
1 /*
2  * (C) Copyright 2009
3  * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
4  *
5  * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 /*
14  * High Level Configuration Options
15  * (easy to change)
16  */
17 #define CONFIG_SPEAR600				/* SPEAr600 SoC */
18 #define CONFIG_X600				/* on X600 board */
19 #define CONFIG_SYS_THUMB_BUILD
20 
21 #include <asm/arch/hardware.h>
22 
23 /* Timer, HZ specific defines */
24 #define CONFIG_SYS_HZ_CLOCK			8300000
25 
26 #define	CONFIG_SYS_TEXT_BASE			0x00800040
27 #define CONFIG_SYS_FLASH_BASE			0xf8000000
28 /* Reserve 8KiB for SPL */
29 #define CONFIG_SPL_PAD_TO			8192	/* decimal for 'dd' */
30 #define CONFIG_SYS_SPL_LEN			CONFIG_SPL_PAD_TO
31 #define CONFIG_SYS_UBOOT_BASE			(CONFIG_SYS_FLASH_BASE + \
32 						 CONFIG_SYS_SPL_LEN)
33 #define CONFIG_SYS_UBOOT_START			CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
35 #define CONFIG_SYS_MONITOR_LEN			0x60000
36 
37 #define CONFIG_ENV_IS_IN_FLASH
38 
39 /* Serial Configuration (PL011) */
40 #define CONFIG_SYS_SERIAL0			0xD0000000
41 #define CONFIG_SYS_SERIAL1			0xD0080000
42 #define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
43 						(void *)CONFIG_SYS_SERIAL1 }
44 #define CONFIG_PL011_SERIAL
45 #define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
46 #define CONFIG_CONS_INDEX			0
47 #define CONFIG_BAUDRATE				115200
48 #define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
49 						  57600, 115200 }
50 #define CONFIG_SYS_LOADS_BAUD_CHANGE
51 
52 /* NOR FLASH config options */
53 #define CONFIG_ST_SMI
54 #define CONFIG_SYS_MAX_FLASH_BANKS		1
55 #define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
56 #define CONFIG_SYS_FLASH_ADDR_BASE		{ CONFIG_SYS_FLASH_BASE }
57 #define CONFIG_SYS_MAX_FLASH_SECT		128
58 #define CONFIG_SYS_FLASH_EMPTY_INFO
59 #define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
60 #define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
61 
62 /* NAND FLASH config options */
63 #define CONFIG_NAND_FSMC
64 #define CONFIG_SYS_NAND_SELF_INIT
65 #define CONFIG_SYS_MAX_NAND_DEVICE		1
66 #define CONFIG_SYS_NAND_BASE			CONFIG_FSMC_NAND_BASE
67 #define CONFIG_MTD_ECC_SOFT
68 #define CONFIG_SYS_FSMC_NAND_8BIT
69 #define CONFIG_SYS_NAND_ONFI_DETECTION
70 #define CONFIG_NAND_ECC_BCH
71 #define CONFIG_BCH
72 
73 /* UBI/UBI config options */
74 #define CONFIG_MTD_DEVICE
75 #define CONFIG_MTD_PARTITIONS
76 #define CONFIG_RBTREE
77 
78 /* Ethernet config options */
79 #define CONFIG_MII
80 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
81 #define CONFIG_PHY_ADDR		0	/* PHY address */
82 #define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
83 #define CONFIG_PHY_MICREL
84 #define CONFIG_PHY_MICREL_KSZ9031
85 
86 #define CONFIG_SPEAR_GPIO
87 
88 /* I2C config options */
89 #define CONFIG_SYS_I2C
90 #define CONFIG_SYS_I2C_BASE			0xD0200000
91 #define CONFIG_SYS_I2C_SPEED			400000
92 #define CONFIG_SYS_I2C_SLAVE			0x02
93 #define CONFIG_I2C_CHIPADDRESS			0x50
94 
95 #define CONFIG_RTC_M41T62	1
96 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
97 
98 /* FPGA config options */
99 #define CONFIG_FPGA
100 #define CONFIG_FPGA_XILINX
101 #define CONFIG_FPGA_SPARTAN3
102 #define CONFIG_FPGA_COUNT	1
103 
104 /* USB EHCI options */
105 #define CONFIG_USB_EHCI
106 #define CONFIG_USB_EHCI_SPEAR
107 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
108 
109 /*
110  * Command support defines
111  */
112 #define CONFIG_CMD_DATE
113 #define CONFIG_CMD_ENV
114 #define CONFIG_CMD_FPGA_LOADMK
115 #define CONFIG_CMD_MTDPARTS
116 #define CONFIG_CMD_NAND
117 #define CONFIG_CMD_SAVES
118 #define CONFIG_CMD_UBIFS
119 #define CONFIG_LZO
120 
121 /* Filesystem support (for USB key) */
122 #define CONFIG_SUPPORT_VFAT
123 #define CONFIG_DOS_PARTITION
124 
125 
126 /*
127  * U-Boot Environment placing definitions.
128  */
129 #define CONFIG_ENV_SECT_SIZE			0x00010000
130 #define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
131 						 CONFIG_SYS_MONITOR_LEN)
132 #define CONFIG_ENV_SIZE				0x02000
133 #define CONFIG_ENV_ADDR_REDUND			(CONFIG_ENV_ADDR + \
134 						 CONFIG_ENV_SECT_SIZE)
135 #define CONFIG_ENV_SIZE_REDUND			(CONFIG_ENV_SIZE)
136 
137 /* Miscellaneous configurable options */
138 #define CONFIG_ARCH_CPU_INIT
139 #define CONFIG_BOOT_PARAMS_ADDR			0x00000100
140 #define CONFIG_CMDLINE_TAG
141 #define CONFIG_SETUP_MEMORY_TAGS
142 #define CONFIG_MISC_INIT_R
143 #define CONFIG_BOARD_LATE_INIT
144 #define CONFIG_MX_CYCLIC		/* enable mdc/mwc commands      */
145 
146 #define CONFIG_SYS_MEMTEST_START		0x00800000
147 #define CONFIG_SYS_MEMTEST_END			0x04000000
148 #define CONFIG_SYS_MALLOC_LEN			(8 << 20)
149 #define CONFIG_SYS_LONGHELP
150 #define CONFIG_CMDLINE_EDITING
151 #define CONFIG_AUTO_COMPLETE
152 #define CONFIG_SYS_CBSIZE			256
153 #define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
154 						 sizeof(CONFIG_SYS_PROMPT) + 16)
155 #define CONFIG_SYS_MAXARGS			16
156 #define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
157 #define CONFIG_SYS_LOAD_ADDR			0x00800000
158 #define CONFIG_SYS_CONSOLE_INFO_QUIET
159 
160 /* Use last 2 lwords in internal SRAM for bootcounter */
161 #define CONFIG_BOOTCOUNT_LIMIT
162 #define CONFIG_SYS_BOOTCOUNT_ADDR		(CONFIG_SRAM_BASE + \
163 						 CONFIG_SRAM_SIZE)
164 
165 #define CONFIG_HOSTNAME				x600
166 #define CONFIG_UBI_PART				ubi0
167 #define CONFIG_UBIFS_VOLUME			rootfs
168 
169 #define MTDIDS_DEFAULT		"nand0=nand"
170 #define MTDPARTS_DEFAULT	"mtdparts=nand:64M(ubi0),64M(ubi1)"
171 
172 #define	CONFIG_EXTRA_ENV_SETTINGS					\
173 	"u-boot_addr=1000000\0"						\
174 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0"		\
175 	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
176 	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
177 		" +${filesize};"					\
178 		"erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
179 		"cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
180 		" ${filesize};"						\
181 		"protect on " __stringify(CONFIG_SYS_MONITOR_BASE)	\
182 		" +${filesize}\0"					\
183 	"upd=run load update\0"						\
184 	"ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0"		\
185 	"part=" __stringify(CONFIG_UBI_PART) "\0"			\
186 	"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0"			\
187 	"load_ubifs=tftp ${kernel_addr} ${ubifs}\0"			\
188 	"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}"	\
189 		" ${filesize}\0"					\
190 	"upd_ubifs=run load_ubifs update_ubifs\0"			\
191 	"init_ubifs=nand erase.part ubi0;ubi part ${part};"		\
192 		"ubi create ${vol} 4000000\0"				\
193 	"netdev=eth0\0"							\
194 	"rootpath=/opt/eldk-4.2/arm\0"					\
195 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
196 		"nfsroot=${serverip}:${rootpath}\0"			\
197 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
198 	"boot_part=0\0"							\
199 	"altbootcmd=if test $boot_part -eq 0;then "			\
200 			"echo Switching to partition 1!;"		\
201 			"setenv boot_part 1;"				\
202 		"else; "						\
203 			"echo Switching to partition 0!;"		\
204 			"setenv boot_part 0;"				\
205 		"fi;"							\
206 		"saveenv;boot\0"					\
207 	"ubifsargs=set bootargs ubi.mtd=ubi${boot_part} "		\
208 		"root=ubi0:rootfs rootfstype=ubifs\0"			\
209 	"kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
210 	"kernel_fs=/boot/uImage \0"					\
211 	"kernel_addr=1000000\0"						\
212 	"dtb=" __stringify(CONFIG_HOSTNAME) "/"				\
213 		__stringify(CONFIG_HOSTNAME) ".dtb\0"			\
214 	"dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0"		\
215 	"dtb_addr=1800000\0"						\
216 	"load_kernel=tftp ${kernel_addr} ${kernel}\0"			\
217 	"load_dtb=tftp ${dtb_addr} ${dtb}\0"				\
218 	"addip=setenv bootargs ${bootargs} "				\
219 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
220 		":${hostname}:${netdev}:off panic=1\0"			\
221 	"addcon=setenv bootargs ${bootargs} console=ttyAMA0,"		\
222 		"${baudrate}\0"						\
223 	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
224 	"net_nfs=run load_dtb load_kernel; "				\
225 		"run nfsargs addip addcon addmtd addmisc;"		\
226 		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
227 	"mtdids=" MTDIDS_DEFAULT "\0"					\
228 	"mtdparts=" MTDPARTS_DEFAULT "\0"				\
229 	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip"		\
230 		" addcon addmisc addmtd;"				\
231 		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
232 	"ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0"	\
233 	"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};"		\
234 		"ubifsload ${dtb_addr} ${dtb_fs};\0"			\
235 	"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon "	\
236 		"addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0"	\
237 	"bootcmd=run nand_ubifs\0"					\
238 	"\0"
239 
240 /* Physical Memory Map */
241 #define CONFIG_NR_DRAM_BANKS			1
242 #define PHYS_SDRAM_1				0x00000000
243 #define PHYS_SDRAM_1_MAXSIZE			0x40000000
244 
245 #define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
246 #define CONFIG_SRAM_BASE			0xd2800000
247 /* Preserve the last 2 lwords for the boot-counter */
248 #define CONFIG_SRAM_SIZE			((8 << 10) - 0x8)
249 #define CONFIG_SYS_INIT_RAM_ADDR		CONFIG_SRAM_BASE
250 #define CONFIG_SYS_INIT_RAM_SIZE		CONFIG_SRAM_SIZE
251 
252 #define CONFIG_SYS_INIT_SP_OFFSET		\
253 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
254 
255 #define CONFIG_SYS_INIT_SP_ADDR			\
256 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
257 
258 /*
259  * SPL related defines
260  */
261 #define CONFIG_SPL_TEXT_BASE		0xd2800b00
262 #define CONFIG_SPL_MAX_SIZE		(CONFIG_SRAM_SIZE - 0xb00)
263 #define	CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/spear"
264 #define CONFIG_SPL_LDSCRIPT	"arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
265 
266 #define CONFIG_SPL_FRAMEWORK
267 
268 /*
269  * Please select/define only one of the following
270  * Each definition corresponds to a supported DDR chip.
271  * DDR configuration is based on the following selection
272  */
273 #define CONFIG_DDR_MT47H64M16		1
274 #define CONFIG_DDR_MT47H32M16		0
275 #define CONFIG_DDR_MT47H128M8		0
276 
277 /*
278  * Synchronous/Asynchronous operation of DDR
279  *
280  * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
281  * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
282  * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
283  */
284 #define CONFIG_DDR_2HCLK		1
285 #define CONFIG_DDR_HCLK			0
286 #define CONFIG_DDR_PLL2			0
287 
288 /*
289  * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
290  * or not. Modify/Add to only these macros to define new boot types
291  */
292 #define USB_BOOT_SUPPORTED		0
293 #define PCIE_BOOT_SUPPORTED		0
294 #define SNOR_BOOT_SUPPORTED		1
295 #define NAND_BOOT_SUPPORTED		1
296 #define PNOR_BOOT_SUPPORTED		0
297 #define TFTP_BOOT_SUPPORTED		0
298 #define UART_BOOT_SUPPORTED		0
299 #define SPI_BOOT_SUPPORTED		0
300 #define I2C_BOOT_SUPPORTED		0
301 #define MMC_BOOT_SUPPORTED		0
302 
303 #endif  /* __CONFIG_H */
304