1995b72ddSStefan Roese /* 2995b72ddSStefan Roese * (C) Copyright 2009 3995b72ddSStefan Roese * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 4995b72ddSStefan Roese * 5995b72ddSStefan Roese * Copyright (C) 2012 Stefan Roese <sr@denx.de> 6995b72ddSStefan Roese * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8995b72ddSStefan Roese */ 9995b72ddSStefan Roese 10995b72ddSStefan Roese #ifndef __CONFIG_H 11995b72ddSStefan Roese #define __CONFIG_H 12995b72ddSStefan Roese 13995b72ddSStefan Roese /* 14995b72ddSStefan Roese * High Level Configuration Options 15995b72ddSStefan Roese * (easy to change) 16995b72ddSStefan Roese */ 17995b72ddSStefan Roese #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 18995b72ddSStefan Roese #define CONFIG_X600 /* on X600 board */ 19995b72ddSStefan Roese 20995b72ddSStefan Roese #include <asm/arch/hardware.h> 21995b72ddSStefan Roese 22995b72ddSStefan Roese /* Timer, HZ specific defines */ 23995b72ddSStefan Roese #define CONFIG_SYS_HZ_CLOCK 8300000 24995b72ddSStefan Roese 25995b72ddSStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800040 26995b72ddSStefan Roese #define CONFIG_SYS_FLASH_BASE 0xf8000000 27995b72ddSStefan Roese /* Reserve 8KiB for SPL */ 28995b72ddSStefan Roese #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 29995b72ddSStefan Roese #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 30995b72ddSStefan Roese #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 31995b72ddSStefan Roese CONFIG_SYS_SPL_LEN) 32995b72ddSStefan Roese #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 33995b72ddSStefan Roese #define CONFIG_SYS_MONITOR_LEN 0x60000 34995b72ddSStefan Roese 35995b72ddSStefan Roese #define CONFIG_ENV_IS_IN_FLASH 36995b72ddSStefan Roese 37995b72ddSStefan Roese /* Serial Configuration (PL011) */ 38995b72ddSStefan Roese #define CONFIG_SYS_SERIAL0 0xD0000000 39995b72ddSStefan Roese #define CONFIG_SYS_SERIAL1 0xD0080000 40995b72ddSStefan Roese #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 41995b72ddSStefan Roese (void *)CONFIG_SYS_SERIAL1 } 42995b72ddSStefan Roese #define CONFIG_PL011_SERIAL 43995b72ddSStefan Roese #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 44995b72ddSStefan Roese #define CONFIG_CONS_INDEX 0 45995b72ddSStefan Roese #define CONFIG_BAUDRATE 115200 46995b72ddSStefan Roese #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 47995b72ddSStefan Roese 57600, 115200 } 48995b72ddSStefan Roese #define CONFIG_SYS_LOADS_BAUD_CHANGE 49995b72ddSStefan Roese 50995b72ddSStefan Roese /* NOR FLASH config options */ 51995b72ddSStefan Roese #define CONFIG_ST_SMI 52995b72ddSStefan Roese #define CONFIG_SYS_MAX_FLASH_BANKS 1 53995b72ddSStefan Roese #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 54995b72ddSStefan Roese #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 55995b72ddSStefan Roese #define CONFIG_SYS_MAX_FLASH_SECT 128 56995b72ddSStefan Roese #define CONFIG_SYS_FLASH_EMPTY_INFO 57995b72ddSStefan Roese #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 58995b72ddSStefan Roese #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 59995b72ddSStefan Roese 60995b72ddSStefan Roese /* NAND FLASH config options */ 61995b72ddSStefan Roese #define CONFIG_NAND_FSMC 62995b72ddSStefan Roese #define CONFIG_SYS_NAND_SELF_INIT 63995b72ddSStefan Roese #define CONFIG_SYS_MAX_NAND_DEVICE 1 64995b72ddSStefan Roese #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 65995b72ddSStefan Roese #define CONFIG_MTD_ECC_SOFT 66995b72ddSStefan Roese #define CONFIG_SYS_FSMC_NAND_8BIT 67995b72ddSStefan Roese #define CONFIG_SYS_NAND_ONFI_DETECTION 68995b72ddSStefan Roese 69995b72ddSStefan Roese /* UBI/UBI config options */ 70995b72ddSStefan Roese #define CONFIG_MTD_DEVICE 71995b72ddSStefan Roese #define CONFIG_MTD_PARTITIONS 72995b72ddSStefan Roese #define CONFIG_RBTREE 73995b72ddSStefan Roese 74995b72ddSStefan Roese /* Ethernet config options */ 75995b72ddSStefan Roese #define CONFIG_MII 76995b72ddSStefan Roese #define CONFIG_DESIGNWARE_ETH 77995b72ddSStefan Roese #define CONFIG_NET_MULTI 781a78d28dSTom Rini #define CONFIG_PHYLIB 79995b72ddSStefan Roese #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 80995b72ddSStefan Roese #define CONFIG_PHY_ADDR 0 /* PHY address */ 81995b72ddSStefan Roese #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 82995b72ddSStefan Roese 83995b72ddSStefan Roese #define CONFIG_SPEAR_GPIO 84995b72ddSStefan Roese 85995b72ddSStefan Roese /* I2C config options */ 86995b72ddSStefan Roese #define CONFIG_HARD_I2C 87995b72ddSStefan Roese #define CONFIG_DW_I2C 88*f93f589cSAlexey Brodkin #define CONFIG_SYS_I2C_BASE 0xD0200000 89995b72ddSStefan Roese #define CONFIG_SYS_I2C_SPEED 400000 90995b72ddSStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x02 91995b72ddSStefan Roese #define CONFIG_I2C_CHIPADDRESS 0x50 92995b72ddSStefan Roese 93995b72ddSStefan Roese #define CONFIG_RTC_M41T62 1 94995b72ddSStefan Roese #define CONFIG_SYS_I2C_RTC_ADDR 0x68 95995b72ddSStefan Roese 96995b72ddSStefan Roese /* FPGA config options */ 97995b72ddSStefan Roese #define CONFIG_FPGA 98995b72ddSStefan Roese #define CONFIG_FPGA_XILINX 99995b72ddSStefan Roese #define CONFIG_FPGA_SPARTAN3 100995b72ddSStefan Roese #define CONFIG_FPGA_COUNT 1 101995b72ddSStefan Roese 102995b72ddSStefan Roese /* 103995b72ddSStefan Roese * Command support defines 104995b72ddSStefan Roese */ 105995b72ddSStefan Roese #define CONFIG_CMD_CACHE 106995b72ddSStefan Roese #define CONFIG_CMD_DATE 107995b72ddSStefan Roese #define CONFIG_CMD_DHCP 108995b72ddSStefan Roese #define CONFIG_CMD_ENV 109995b72ddSStefan Roese #define CONFIG_CMD_FPGA 110995b72ddSStefan Roese #define CONFIG_CMD_GPIO 111995b72ddSStefan Roese #define CONFIG_CMD_I2C 112995b72ddSStefan Roese #define CONFIG_CMD_MEMORY 113995b72ddSStefan Roese #define CONFIG_CMD_MII 114995b72ddSStefan Roese #define CONFIG_CMD_MTDPARTS 115995b72ddSStefan Roese #define CONFIG_CMD_NAND 116995b72ddSStefan Roese #define CONFIG_CMD_NET 117995b72ddSStefan Roese #define CONFIG_CMD_PING 118995b72ddSStefan Roese #define CONFIG_CMD_RUN 119995b72ddSStefan Roese #define CONFIG_CMD_SAVES 120995b72ddSStefan Roese #define CONFIG_CMD_UBI 121995b72ddSStefan Roese #define CONFIG_CMD_UBIFS 122995b72ddSStefan Roese #define CONFIG_LZO 123995b72ddSStefan Roese 124995b72ddSStefan Roese /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 125995b72ddSStefan Roese #include <config_cmd_default.h> 126995b72ddSStefan Roese 127995b72ddSStefan Roese #define CONFIG_BOOTDELAY 3 128995b72ddSStefan Roese 129995b72ddSStefan Roese #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 130995b72ddSStefan Roese #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 131995b72ddSStefan Roese 132995b72ddSStefan Roese /* 133995b72ddSStefan Roese * U-Boot Environment placing definitions. 134995b72ddSStefan Roese */ 135995b72ddSStefan Roese #define CONFIG_ENV_SECT_SIZE 0x00010000 136995b72ddSStefan Roese #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 137995b72ddSStefan Roese CONFIG_SYS_MONITOR_LEN) 138995b72ddSStefan Roese #define CONFIG_ENV_SIZE 0x02000 139995b72ddSStefan Roese #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 140995b72ddSStefan Roese CONFIG_ENV_SECT_SIZE) 141995b72ddSStefan Roese #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 142995b72ddSStefan Roese 143995b72ddSStefan Roese /* Miscellaneous configurable options */ 144995b72ddSStefan Roese #define CONFIG_ARCH_CPU_INIT 145995b72ddSStefan Roese #define CONFIG_DISPLAY_CPUINFO 146995b72ddSStefan Roese #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 147995b72ddSStefan Roese #define CONFIG_CMDLINE_TAG 148995b72ddSStefan Roese #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ 149995b72ddSStefan Roese #define CONFIG_SETUP_MEMORY_TAGS 150995b72ddSStefan Roese #define CONFIG_MISC_INIT_R 151995b72ddSStefan Roese #define CONFIG_BOARD_LATE_INIT 152995b72ddSStefan Roese #define CONFIG_LOOPW /* enable loopw command */ 153995b72ddSStefan Roese #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 154995b72ddSStefan Roese #define CONFIG_ZERO_BOOTDELAY_CHECK 155995b72ddSStefan Roese #define CONFIG_AUTOBOOT_KEYED 156995b72ddSStefan Roese #define CONFIG_AUTOBOOT_STOP_STR " " 157995b72ddSStefan Roese #define CONFIG_AUTOBOOT_PROMPT \ 158995b72ddSStefan Roese "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay 159995b72ddSStefan Roese 160995b72ddSStefan Roese #define CONFIG_SYS_MEMTEST_START 0x00800000 161995b72ddSStefan Roese #define CONFIG_SYS_MEMTEST_END 0x04000000 162995b72ddSStefan Roese #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 163995b72ddSStefan Roese #define CONFIG_IDENT_STRING "-SPEAr" 164995b72ddSStefan Roese #define CONFIG_SYS_LONGHELP 165995b72ddSStefan Roese #define CONFIG_SYS_PROMPT "X600> " 166995b72ddSStefan Roese #define CONFIG_CMDLINE_EDITING 167995b72ddSStefan Roese #define CONFIG_SYS_CBSIZE 256 168995b72ddSStefan Roese #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 169995b72ddSStefan Roese sizeof(CONFIG_SYS_PROMPT) + 16) 170995b72ddSStefan Roese #define CONFIG_SYS_MAXARGS 16 171995b72ddSStefan Roese #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 172995b72ddSStefan Roese #define CONFIG_SYS_LOAD_ADDR 0x00800000 173995b72ddSStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET 174995b72ddSStefan Roese 175995b72ddSStefan Roese /* Use last 2 lwords in internal SRAM for bootcounter */ 176995b72ddSStefan Roese #define CONFIG_BOOTCOUNT_LIMIT 177995b72ddSStefan Roese #define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8 178995b72ddSStefan Roese 179995b72ddSStefan Roese #define CONFIG_HOSTNAME x600 180995b72ddSStefan Roese #define CONFIG_UBI_PART ubi0 181995b72ddSStefan Roese #define CONFIG_UBIFS_VOLUME rootfs 182995b72ddSStefan Roese 183995b72ddSStefan Roese #define xstr(s) str(s) 184995b72ddSStefan Roese #define str(s) #s 185995b72ddSStefan Roese 186995b72ddSStefan Roese #define MTDIDS_DEFAULT "nand0=nand" 187995b72ddSStefan Roese #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" 188995b72ddSStefan Roese 189995b72ddSStefan Roese #define CONFIG_EXTRA_ENV_SETTINGS \ 190995b72ddSStefan Roese "u-boot_addr=1000000\0" \ 191995b72ddSStefan Roese "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \ 192995b72ddSStefan Roese "load=tftp ${u-boot_addr} ${u-boot}\0" \ 193995b72ddSStefan Roese "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\ 194995b72ddSStefan Roese "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 195995b72ddSStefan Roese "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \ 196995b72ddSStefan Roese " ${filesize};" \ 197995b72ddSStefan Roese "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \ 198995b72ddSStefan Roese " +${filesize}\0" \ 199995b72ddSStefan Roese "upd=run load update\0" \ 200995b72ddSStefan Roese "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \ 201995b72ddSStefan Roese "part=" xstr(CONFIG_UBI_PART) "\0" \ 202995b72ddSStefan Roese "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \ 203995b72ddSStefan Roese "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 204995b72ddSStefan Roese "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 205995b72ddSStefan Roese " ${filesize}\0" \ 206995b72ddSStefan Roese "upd_ubifs=run load_ubifs update_ubifs\0" \ 207995b72ddSStefan Roese "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 208995b72ddSStefan Roese "ubi create ${vol} 4000000\0" \ 209995b72ddSStefan Roese "netdev=eth0\0" \ 210995b72ddSStefan Roese "rootpath=/opt/eldk-4.2/arm\0" \ 211995b72ddSStefan Roese "nfsargs=setenv bootargs root=/dev/nfs rw " \ 212995b72ddSStefan Roese "nfsroot=${serverip}:${rootpath}\0" \ 213995b72ddSStefan Roese "ramargs=setenv bootargs root=/dev/ram rw\0" \ 214995b72ddSStefan Roese "boot_part=0\0" \ 215995b72ddSStefan Roese "altbootcmd=if test $boot_part -eq 0;then " \ 216995b72ddSStefan Roese "echo Switching to partition 1!;" \ 217995b72ddSStefan Roese "setenv boot_part 1;" \ 218995b72ddSStefan Roese "else; " \ 219995b72ddSStefan Roese "echo Switching to partition 0!;" \ 220995b72ddSStefan Roese "setenv boot_part 0;" \ 221995b72ddSStefan Roese "fi;" \ 222995b72ddSStefan Roese "saveenv;boot\0" \ 223995b72ddSStefan Roese "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 224995b72ddSStefan Roese "root=ubi0:rootfs rootfstype=ubifs\0" \ 225995b72ddSStefan Roese "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ 226995b72ddSStefan Roese "kernel_fs=/boot/uImage \0" \ 227995b72ddSStefan Roese "kernel_addr=1000000\0" \ 228995b72ddSStefan Roese "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ 229995b72ddSStefan Roese "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ 230995b72ddSStefan Roese "dtb_addr=1800000\0" \ 231995b72ddSStefan Roese "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 232995b72ddSStefan Roese "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 233995b72ddSStefan Roese "addip=setenv bootargs ${bootargs} " \ 234995b72ddSStefan Roese "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 235995b72ddSStefan Roese ":${hostname}:${netdev}:off panic=1\0" \ 236995b72ddSStefan Roese "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 237995b72ddSStefan Roese "${baudrate}\0" \ 238995b72ddSStefan Roese "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 239995b72ddSStefan Roese "net_nfs=run load_dtb load_kernel; " \ 240995b72ddSStefan Roese "run nfsargs addip addcon addmtd addmisc;" \ 241995b72ddSStefan Roese "bootm ${kernel_addr} - ${dtb_addr}\0" \ 242995b72ddSStefan Roese "mtdids=" MTDIDS_DEFAULT "\0" \ 243995b72ddSStefan Roese "mtdparts=" MTDPARTS_DEFAULT "\0" \ 244995b72ddSStefan Roese "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 245995b72ddSStefan Roese " addcon addmisc addmtd;" \ 246995b72ddSStefan Roese "bootm ${kernel_addr} - ${dtb_addr}\0" \ 247949a7710SJoe Hershberger "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ 248995b72ddSStefan Roese "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 249995b72ddSStefan Roese "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 250995b72ddSStefan Roese "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 251995b72ddSStefan Roese "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 252995b72ddSStefan Roese "bootcmd=run nand_ubifs\0" \ 253995b72ddSStefan Roese "\0" 254995b72ddSStefan Roese 255995b72ddSStefan Roese /* Stack sizes */ 256995b72ddSStefan Roese #define CONFIG_STACKSIZE (512 * 1024) 257995b72ddSStefan Roese 258995b72ddSStefan Roese /* Physical Memory Map */ 259995b72ddSStefan Roese #define CONFIG_NR_DRAM_BANKS 1 260995b72ddSStefan Roese #define PHYS_SDRAM_1 0x00000000 261995b72ddSStefan Roese #define PHYS_SDRAM_1_MAXSIZE 0x40000000 262995b72ddSStefan Roese 263995b72ddSStefan Roese #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 264995b72ddSStefan Roese #define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 265995b72ddSStefan Roese #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 266995b72ddSStefan Roese 267995b72ddSStefan Roese #define CONFIG_SYS_INIT_SP_OFFSET \ 268995b72ddSStefan Roese (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 269995b72ddSStefan Roese 270995b72ddSStefan Roese #define CONFIG_SYS_INIT_SP_ADDR \ 271995b72ddSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 272995b72ddSStefan Roese 273995b72ddSStefan Roese /* 274995b72ddSStefan Roese * SPL related defines 275995b72ddSStefan Roese */ 276995b72ddSStefan Roese #define CONFIG_SPL 277995b72ddSStefan Roese #define CONFIG_SPL_TEXT_BASE 0xd2800b00 278995b72ddSStefan Roese #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 279995b72ddSStefan Roese #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" 280995b72ddSStefan Roese 281995b72ddSStefan Roese #define CONFIG_SPL_SERIAL_SUPPORT 282995b72ddSStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ 283995b72ddSStefan Roese #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ 284995b72ddSStefan Roese #define CONFIG_SPL_NO_PRINTF 285995b72ddSStefan Roese 286995b72ddSStefan Roese /* 287995b72ddSStefan Roese * Please select/define only one of the following 288995b72ddSStefan Roese * Each definition corresponds to a supported DDR chip. 289995b72ddSStefan Roese * DDR configuration is based on the following selection 290995b72ddSStefan Roese */ 291995b72ddSStefan Roese #define CONFIG_DDR_MT47H64M16 1 292995b72ddSStefan Roese #define CONFIG_DDR_MT47H32M16 0 293995b72ddSStefan Roese #define CONFIG_DDR_MT47H128M8 0 294995b72ddSStefan Roese 295995b72ddSStefan Roese /* 296995b72ddSStefan Roese * Synchronous/Asynchronous operation of DDR 297995b72ddSStefan Roese * 298995b72ddSStefan Roese * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 299995b72ddSStefan Roese * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 300995b72ddSStefan Roese * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 301995b72ddSStefan Roese */ 302995b72ddSStefan Roese #define CONFIG_DDR_2HCLK 1 303995b72ddSStefan Roese #define CONFIG_DDR_HCLK 0 304995b72ddSStefan Roese #define CONFIG_DDR_PLL2 0 305995b72ddSStefan Roese 306995b72ddSStefan Roese /* 307995b72ddSStefan Roese * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 308995b72ddSStefan Roese * or not. Modify/Add to only these macros to define new boot types 309995b72ddSStefan Roese */ 310995b72ddSStefan Roese #define USB_BOOT_SUPPORTED 0 311995b72ddSStefan Roese #define PCIE_BOOT_SUPPORTED 0 312995b72ddSStefan Roese #define SNOR_BOOT_SUPPORTED 1 313995b72ddSStefan Roese #define NAND_BOOT_SUPPORTED 1 314995b72ddSStefan Roese #define PNOR_BOOT_SUPPORTED 0 315995b72ddSStefan Roese #define TFTP_BOOT_SUPPORTED 0 316995b72ddSStefan Roese #define UART_BOOT_SUPPORTED 0 317995b72ddSStefan Roese #define SPI_BOOT_SUPPORTED 0 318995b72ddSStefan Roese #define I2C_BOOT_SUPPORTED 0 319995b72ddSStefan Roese #define MMC_BOOT_SUPPORTED 0 320995b72ddSStefan Roese 321995b72ddSStefan Roese #endif /* __CONFIG_H */ 322