1*995b72ddSStefan Roese /* 2*995b72ddSStefan Roese * (C) Copyright 2009 3*995b72ddSStefan Roese * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> 4*995b72ddSStefan Roese * 5*995b72ddSStefan Roese * Copyright (C) 2012 Stefan Roese <sr@denx.de> 6*995b72ddSStefan Roese * 7*995b72ddSStefan Roese * See file CREDITS for list of people who contributed to this 8*995b72ddSStefan Roese * project. 9*995b72ddSStefan Roese * 10*995b72ddSStefan Roese * This program is free software; you can redistribute it and/or 11*995b72ddSStefan Roese * modify it under the terms of the GNU General Public License as 12*995b72ddSStefan Roese * published by the Free Software Foundation; either version 2 of 13*995b72ddSStefan Roese * the License, or (at your option) any later version. 14*995b72ddSStefan Roese * 15*995b72ddSStefan Roese * This program is distributed in the hope that it will be useful, 16*995b72ddSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*995b72ddSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*995b72ddSStefan Roese * GNU General Public License for more details. 19*995b72ddSStefan Roese * 20*995b72ddSStefan Roese * You should have received a copy of the GNU General Public License 21*995b72ddSStefan Roese * along with this program; if not, write to the Free Software 22*995b72ddSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23*995b72ddSStefan Roese * MA 02111-1307 USA 24*995b72ddSStefan Roese */ 25*995b72ddSStefan Roese 26*995b72ddSStefan Roese #ifndef __CONFIG_H 27*995b72ddSStefan Roese #define __CONFIG_H 28*995b72ddSStefan Roese 29*995b72ddSStefan Roese /* 30*995b72ddSStefan Roese * High Level Configuration Options 31*995b72ddSStefan Roese * (easy to change) 32*995b72ddSStefan Roese */ 33*995b72ddSStefan Roese #define CONFIG_SPEAR600 /* SPEAr600 SoC */ 34*995b72ddSStefan Roese #define CONFIG_X600 /* on X600 board */ 35*995b72ddSStefan Roese 36*995b72ddSStefan Roese #include <asm/arch/hardware.h> 37*995b72ddSStefan Roese 38*995b72ddSStefan Roese /* Timer, HZ specific defines */ 39*995b72ddSStefan Roese #define CONFIG_SYS_HZ 1000 40*995b72ddSStefan Roese #define CONFIG_SYS_HZ_CLOCK 8300000 41*995b72ddSStefan Roese 42*995b72ddSStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800040 43*995b72ddSStefan Roese #define CONFIG_SYS_FLASH_BASE 0xf8000000 44*995b72ddSStefan Roese /* Reserve 8KiB for SPL */ 45*995b72ddSStefan Roese #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ 46*995b72ddSStefan Roese #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO 47*995b72ddSStefan Roese #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 48*995b72ddSStefan Roese CONFIG_SYS_SPL_LEN) 49*995b72ddSStefan Roese #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 50*995b72ddSStefan Roese #define CONFIG_SYS_MONITOR_LEN 0x60000 51*995b72ddSStefan Roese 52*995b72ddSStefan Roese #define CONFIG_ENV_IS_IN_FLASH 53*995b72ddSStefan Roese 54*995b72ddSStefan Roese /* Serial Configuration (PL011) */ 55*995b72ddSStefan Roese #define CONFIG_SYS_SERIAL0 0xD0000000 56*995b72ddSStefan Roese #define CONFIG_SYS_SERIAL1 0xD0080000 57*995b72ddSStefan Roese #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ 58*995b72ddSStefan Roese (void *)CONFIG_SYS_SERIAL1 } 59*995b72ddSStefan Roese #define CONFIG_PL011_SERIAL 60*995b72ddSStefan Roese #define CONFIG_PL011_CLOCK (48 * 1000 * 1000) 61*995b72ddSStefan Roese #define CONFIG_CONS_INDEX 0 62*995b72ddSStefan Roese #define CONFIG_BAUDRATE 115200 63*995b72ddSStefan Roese #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ 64*995b72ddSStefan Roese 57600, 115200 } 65*995b72ddSStefan Roese #define CONFIG_SYS_LOADS_BAUD_CHANGE 66*995b72ddSStefan Roese 67*995b72ddSStefan Roese /* NOR FLASH config options */ 68*995b72ddSStefan Roese #define CONFIG_ST_SMI 69*995b72ddSStefan Roese #define CONFIG_SYS_MAX_FLASH_BANKS 1 70*995b72ddSStefan Roese #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 71*995b72ddSStefan Roese #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } 72*995b72ddSStefan Roese #define CONFIG_SYS_MAX_FLASH_SECT 128 73*995b72ddSStefan Roese #define CONFIG_SYS_FLASH_EMPTY_INFO 74*995b72ddSStefan Roese #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) 75*995b72ddSStefan Roese #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) 76*995b72ddSStefan Roese 77*995b72ddSStefan Roese /* NAND FLASH config options */ 78*995b72ddSStefan Roese #define CONFIG_NAND_FSMC 79*995b72ddSStefan Roese #define CONFIG_SYS_NAND_SELF_INIT 80*995b72ddSStefan Roese #define CONFIG_SYS_MAX_NAND_DEVICE 1 81*995b72ddSStefan Roese #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE 82*995b72ddSStefan Roese #define CONFIG_MTD_ECC_SOFT 83*995b72ddSStefan Roese #define CONFIG_SYS_FSMC_NAND_8BIT 84*995b72ddSStefan Roese #define CONFIG_SYS_NAND_ONFI_DETECTION 85*995b72ddSStefan Roese 86*995b72ddSStefan Roese /* UBI/UBI config options */ 87*995b72ddSStefan Roese #define CONFIG_MTD_DEVICE 88*995b72ddSStefan Roese #define CONFIG_MTD_PARTITIONS 89*995b72ddSStefan Roese #define CONFIG_RBTREE 90*995b72ddSStefan Roese 91*995b72ddSStefan Roese /* Ethernet config options */ 92*995b72ddSStefan Roese #define CONFIG_MII 93*995b72ddSStefan Roese #define CONFIG_DESIGNWARE_ETH 94*995b72ddSStefan Roese #define CONFIG_DW_SEARCH_PHY 95*995b72ddSStefan Roese #define CONFIG_NET_MULTI 96*995b72ddSStefan Roese #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ 97*995b72ddSStefan Roese #define CONFIG_DW_AUTONEG 98*995b72ddSStefan Roese #define CONFIG_PHY_ADDR 0 /* PHY address */ 99*995b72ddSStefan Roese #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 100*995b72ddSStefan Roese 101*995b72ddSStefan Roese #define CONFIG_SPEAR_GPIO 102*995b72ddSStefan Roese 103*995b72ddSStefan Roese /* I2C config options */ 104*995b72ddSStefan Roese #define CONFIG_HARD_I2C 105*995b72ddSStefan Roese #define CONFIG_DW_I2C 106*995b72ddSStefan Roese #define CONFIG_SYS_I2C_SPEED 400000 107*995b72ddSStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x02 108*995b72ddSStefan Roese #define CONFIG_I2C_CHIPADDRESS 0x50 109*995b72ddSStefan Roese 110*995b72ddSStefan Roese #define CONFIG_RTC_M41T62 1 111*995b72ddSStefan Roese #define CONFIG_SYS_I2C_RTC_ADDR 0x68 112*995b72ddSStefan Roese 113*995b72ddSStefan Roese /* FPGA config options */ 114*995b72ddSStefan Roese #define CONFIG_FPGA 115*995b72ddSStefan Roese #define CONFIG_FPGA_XILINX 116*995b72ddSStefan Roese #define CONFIG_FPGA_SPARTAN3 117*995b72ddSStefan Roese #define CONFIG_FPGA_COUNT 1 118*995b72ddSStefan Roese 119*995b72ddSStefan Roese /* 120*995b72ddSStefan Roese * Command support defines 121*995b72ddSStefan Roese */ 122*995b72ddSStefan Roese #define CONFIG_CMD_CACHE 123*995b72ddSStefan Roese #define CONFIG_CMD_DATE 124*995b72ddSStefan Roese #define CONFIG_CMD_DHCP 125*995b72ddSStefan Roese #define CONFIG_CMD_ENV 126*995b72ddSStefan Roese #define CONFIG_CMD_FPGA 127*995b72ddSStefan Roese #define CONFIG_CMD_GPIO 128*995b72ddSStefan Roese #define CONFIG_CMD_I2C 129*995b72ddSStefan Roese #define CONFIG_CMD_MEMORY 130*995b72ddSStefan Roese #define CONFIG_CMD_MII 131*995b72ddSStefan Roese #define CONFIG_CMD_MTDPARTS 132*995b72ddSStefan Roese #define CONFIG_CMD_NAND 133*995b72ddSStefan Roese #define CONFIG_CMD_NET 134*995b72ddSStefan Roese #define CONFIG_CMD_PING 135*995b72ddSStefan Roese #define CONFIG_CMD_RUN 136*995b72ddSStefan Roese #define CONFIG_CMD_SAVES 137*995b72ddSStefan Roese #define CONFIG_CMD_UBI 138*995b72ddSStefan Roese #define CONFIG_CMD_UBIFS 139*995b72ddSStefan Roese #define CONFIG_LZO 140*995b72ddSStefan Roese 141*995b72ddSStefan Roese /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 142*995b72ddSStefan Roese #include <config_cmd_default.h> 143*995b72ddSStefan Roese 144*995b72ddSStefan Roese #define CONFIG_BOOTDELAY 3 145*995b72ddSStefan Roese 146*995b72ddSStefan Roese #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ 147*995b72ddSStefan Roese #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 148*995b72ddSStefan Roese 149*995b72ddSStefan Roese /* 150*995b72ddSStefan Roese * U-Boot Environment placing definitions. 151*995b72ddSStefan Roese */ 152*995b72ddSStefan Roese #define CONFIG_ENV_SECT_SIZE 0x00010000 153*995b72ddSStefan Roese #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 154*995b72ddSStefan Roese CONFIG_SYS_MONITOR_LEN) 155*995b72ddSStefan Roese #define CONFIG_ENV_SIZE 0x02000 156*995b72ddSStefan Roese #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ 157*995b72ddSStefan Roese CONFIG_ENV_SECT_SIZE) 158*995b72ddSStefan Roese #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 159*995b72ddSStefan Roese 160*995b72ddSStefan Roese /* Miscellaneous configurable options */ 161*995b72ddSStefan Roese #define CONFIG_ARCH_CPU_INIT 162*995b72ddSStefan Roese #define CONFIG_DISPLAY_CPUINFO 163*995b72ddSStefan Roese #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 164*995b72ddSStefan Roese #define CONFIG_CMDLINE_TAG 165*995b72ddSStefan Roese #define CONFIG_OF_LIBFDT /* enable passing of devicetree */ 166*995b72ddSStefan Roese #define CONFIG_SETUP_MEMORY_TAGS 167*995b72ddSStefan Roese #define CONFIG_MISC_INIT_R 168*995b72ddSStefan Roese #define CONFIG_BOARD_LATE_INIT 169*995b72ddSStefan Roese #define CONFIG_LOOPW /* enable loopw command */ 170*995b72ddSStefan Roese #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ 171*995b72ddSStefan Roese #define CONFIG_ZERO_BOOTDELAY_CHECK 172*995b72ddSStefan Roese #define CONFIG_AUTOBOOT_KEYED 173*995b72ddSStefan Roese #define CONFIG_AUTOBOOT_STOP_STR " " 174*995b72ddSStefan Roese #define CONFIG_AUTOBOOT_PROMPT \ 175*995b72ddSStefan Roese "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay 176*995b72ddSStefan Roese 177*995b72ddSStefan Roese #define CONFIG_SYS_MEMTEST_START 0x00800000 178*995b72ddSStefan Roese #define CONFIG_SYS_MEMTEST_END 0x04000000 179*995b72ddSStefan Roese #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 180*995b72ddSStefan Roese #define CONFIG_IDENT_STRING "-SPEAr" 181*995b72ddSStefan Roese #define CONFIG_SYS_LONGHELP 182*995b72ddSStefan Roese #define CONFIG_SYS_PROMPT "X600> " 183*995b72ddSStefan Roese #define CONFIG_CMDLINE_EDITING 184*995b72ddSStefan Roese #define CONFIG_SYS_CBSIZE 256 185*995b72ddSStefan Roese #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 186*995b72ddSStefan Roese sizeof(CONFIG_SYS_PROMPT) + 16) 187*995b72ddSStefan Roese #define CONFIG_SYS_MAXARGS 16 188*995b72ddSStefan Roese #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 189*995b72ddSStefan Roese #define CONFIG_SYS_LOAD_ADDR 0x00800000 190*995b72ddSStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET 191*995b72ddSStefan Roese #define CONFIG_SYS_64BIT_VSPRINTF 192*995b72ddSStefan Roese 193*995b72ddSStefan Roese /* Use last 2 lwords in internal SRAM for bootcounter */ 194*995b72ddSStefan Roese #define CONFIG_BOOTCOUNT_LIMIT 195*995b72ddSStefan Roese #define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8 196*995b72ddSStefan Roese 197*995b72ddSStefan Roese #define CONFIG_HOSTNAME x600 198*995b72ddSStefan Roese #define CONFIG_UBI_PART ubi0 199*995b72ddSStefan Roese #define CONFIG_UBIFS_VOLUME rootfs 200*995b72ddSStefan Roese 201*995b72ddSStefan Roese #define xstr(s) str(s) 202*995b72ddSStefan Roese #define str(s) #s 203*995b72ddSStefan Roese 204*995b72ddSStefan Roese #define MTDIDS_DEFAULT "nand0=nand" 205*995b72ddSStefan Roese #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" 206*995b72ddSStefan Roese 207*995b72ddSStefan Roese #define CONFIG_EXTRA_ENV_SETTINGS \ 208*995b72ddSStefan Roese "u-boot_addr=1000000\0" \ 209*995b72ddSStefan Roese "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \ 210*995b72ddSStefan Roese "load=tftp ${u-boot_addr} ${u-boot}\0" \ 211*995b72ddSStefan Roese "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\ 212*995b72ddSStefan Roese "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ 213*995b72ddSStefan Roese "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \ 214*995b72ddSStefan Roese " ${filesize};" \ 215*995b72ddSStefan Roese "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \ 216*995b72ddSStefan Roese " +${filesize}\0" \ 217*995b72ddSStefan Roese "upd=run load update\0" \ 218*995b72ddSStefan Roese "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \ 219*995b72ddSStefan Roese "part=" xstr(CONFIG_UBI_PART) "\0" \ 220*995b72ddSStefan Roese "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \ 221*995b72ddSStefan Roese "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ 222*995b72ddSStefan Roese "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ 223*995b72ddSStefan Roese " ${filesize}\0" \ 224*995b72ddSStefan Roese "upd_ubifs=run load_ubifs update_ubifs\0" \ 225*995b72ddSStefan Roese "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ 226*995b72ddSStefan Roese "ubi create ${vol} 4000000\0" \ 227*995b72ddSStefan Roese "netdev=eth0\0" \ 228*995b72ddSStefan Roese "rootpath=/opt/eldk-4.2/arm\0" \ 229*995b72ddSStefan Roese "nfsargs=setenv bootargs root=/dev/nfs rw " \ 230*995b72ddSStefan Roese "nfsroot=${serverip}:${rootpath}\0" \ 231*995b72ddSStefan Roese "ramargs=setenv bootargs root=/dev/ram rw\0" \ 232*995b72ddSStefan Roese "boot_part=0\0" \ 233*995b72ddSStefan Roese "altbootcmd=if test $boot_part -eq 0;then " \ 234*995b72ddSStefan Roese "echo Switching to partition 1!;" \ 235*995b72ddSStefan Roese "setenv boot_part 1;" \ 236*995b72ddSStefan Roese "else; " \ 237*995b72ddSStefan Roese "echo Switching to partition 0!;" \ 238*995b72ddSStefan Roese "setenv boot_part 0;" \ 239*995b72ddSStefan Roese "fi;" \ 240*995b72ddSStefan Roese "saveenv;boot\0" \ 241*995b72ddSStefan Roese "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ 242*995b72ddSStefan Roese "root=ubi0:rootfs rootfstype=ubifs\0" \ 243*995b72ddSStefan Roese "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ 244*995b72ddSStefan Roese "kernel_fs=/boot/uImage \0" \ 245*995b72ddSStefan Roese "kernel_addr=1000000\0" \ 246*995b72ddSStefan Roese "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ 247*995b72ddSStefan Roese "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ 248*995b72ddSStefan Roese "dtb_addr=1800000\0" \ 249*995b72ddSStefan Roese "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ 250*995b72ddSStefan Roese "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ 251*995b72ddSStefan Roese "addip=setenv bootargs ${bootargs} " \ 252*995b72ddSStefan Roese "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 253*995b72ddSStefan Roese ":${hostname}:${netdev}:off panic=1\0" \ 254*995b72ddSStefan Roese "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ 255*995b72ddSStefan Roese "${baudrate}\0" \ 256*995b72ddSStefan Roese "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 257*995b72ddSStefan Roese "net_nfs=run load_dtb load_kernel; " \ 258*995b72ddSStefan Roese "run nfsargs addip addcon addmtd addmisc;" \ 259*995b72ddSStefan Roese "bootm ${kernel_addr} - ${dtb_addr}\0" \ 260*995b72ddSStefan Roese "mtdids=" MTDIDS_DEFAULT "\0" \ 261*995b72ddSStefan Roese "mtdparts=" MTDPARTS_DEFAULT "\0" \ 262*995b72ddSStefan Roese "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ 263*995b72ddSStefan Roese " addcon addmisc addmtd;" \ 264*995b72ddSStefan Roese "bootm ${kernel_addr} - ${dtb_addr}\0" \ 265*995b72ddSStefan Roese "ubifs_mount=ubi part ubi${boot_part};ubifsmount rootfs\0" \ 266*995b72ddSStefan Roese "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ 267*995b72ddSStefan Roese "ubifsload ${dtb_addr} ${dtb_fs};\0" \ 268*995b72ddSStefan Roese "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ 269*995b72ddSStefan Roese "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ 270*995b72ddSStefan Roese "bootcmd=run nand_ubifs\0" \ 271*995b72ddSStefan Roese "\0" 272*995b72ddSStefan Roese 273*995b72ddSStefan Roese /* Stack sizes */ 274*995b72ddSStefan Roese #define CONFIG_STACKSIZE (512 * 1024) 275*995b72ddSStefan Roese 276*995b72ddSStefan Roese /* Physical Memory Map */ 277*995b72ddSStefan Roese #define CONFIG_NR_DRAM_BANKS 1 278*995b72ddSStefan Roese #define PHYS_SDRAM_1 0x00000000 279*995b72ddSStefan Roese #define PHYS_SDRAM_1_MAXSIZE 0x40000000 280*995b72ddSStefan Roese 281*995b72ddSStefan Roese #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 282*995b72ddSStefan Roese #define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 283*995b72ddSStefan Roese #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 284*995b72ddSStefan Roese 285*995b72ddSStefan Roese #define CONFIG_SYS_INIT_SP_OFFSET \ 286*995b72ddSStefan Roese (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 287*995b72ddSStefan Roese 288*995b72ddSStefan Roese #define CONFIG_SYS_INIT_SP_ADDR \ 289*995b72ddSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 290*995b72ddSStefan Roese 291*995b72ddSStefan Roese /* 292*995b72ddSStefan Roese * SPL related defines 293*995b72ddSStefan Roese */ 294*995b72ddSStefan Roese #define CONFIG_SPL 295*995b72ddSStefan Roese #define CONFIG_SPL_TEXT_BASE 0xd2800b00 296*995b72ddSStefan Roese #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" 297*995b72ddSStefan Roese #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" 298*995b72ddSStefan Roese 299*995b72ddSStefan Roese #define CONFIG_SPL_SERIAL_SUPPORT 300*995b72ddSStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ 301*995b72ddSStefan Roese #define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ 302*995b72ddSStefan Roese #define CONFIG_SPL_NO_PRINTF 303*995b72ddSStefan Roese 304*995b72ddSStefan Roese /* 305*995b72ddSStefan Roese * Please select/define only one of the following 306*995b72ddSStefan Roese * Each definition corresponds to a supported DDR chip. 307*995b72ddSStefan Roese * DDR configuration is based on the following selection 308*995b72ddSStefan Roese */ 309*995b72ddSStefan Roese #define CONFIG_DDR_MT47H64M16 1 310*995b72ddSStefan Roese #define CONFIG_DDR_MT47H32M16 0 311*995b72ddSStefan Roese #define CONFIG_DDR_MT47H128M8 0 312*995b72ddSStefan Roese 313*995b72ddSStefan Roese /* 314*995b72ddSStefan Roese * Synchronous/Asynchronous operation of DDR 315*995b72ddSStefan Roese * 316*995b72ddSStefan Roese * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation 317*995b72ddSStefan Roese * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation 318*995b72ddSStefan Roese * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation 319*995b72ddSStefan Roese */ 320*995b72ddSStefan Roese #define CONFIG_DDR_2HCLK 1 321*995b72ddSStefan Roese #define CONFIG_DDR_HCLK 0 322*995b72ddSStefan Roese #define CONFIG_DDR_PLL2 0 323*995b72ddSStefan Roese 324*995b72ddSStefan Roese /* 325*995b72ddSStefan Roese * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported 326*995b72ddSStefan Roese * or not. Modify/Add to only these macros to define new boot types 327*995b72ddSStefan Roese */ 328*995b72ddSStefan Roese #define USB_BOOT_SUPPORTED 0 329*995b72ddSStefan Roese #define PCIE_BOOT_SUPPORTED 0 330*995b72ddSStefan Roese #define SNOR_BOOT_SUPPORTED 1 331*995b72ddSStefan Roese #define NAND_BOOT_SUPPORTED 1 332*995b72ddSStefan Roese #define PNOR_BOOT_SUPPORTED 0 333*995b72ddSStefan Roese #define TFTP_BOOT_SUPPORTED 0 334*995b72ddSStefan Roese #define UART_BOOT_SUPPORTED 0 335*995b72ddSStefan Roese #define SPI_BOOT_SUPPORTED 0 336*995b72ddSStefan Roese #define I2C_BOOT_SUPPORTED 0 337*995b72ddSStefan Roese #define MMC_BOOT_SUPPORTED 0 338*995b72ddSStefan Roese 339*995b72ddSStefan Roese #endif /* __CONFIG_H */ 340