1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2018 Allied Telesis Labs 4 */ 5 6 #ifndef _CONFIG_X530_H 7 #define _CONFIG_X530_H 8 9 /* 10 * High Level Configuration Options (easy to change) 11 */ 12 13 #define CONFIG_DISPLAY_BOARDINFO_LATE 14 15 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 16 17 /* 18 * NS16550 Configuration 19 */ 20 #define CONFIG_SYS_NS16550_SERIAL 21 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK 22 #if !defined(CONFIG_DM_SERIAL) 23 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 24 #define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE 25 #endif 26 27 /* 28 * Serial Port configuration 29 * The following definitions let you select what serial you want to use 30 * for your console driver. 31 */ 32 33 #define CONFIG_CONS_INDEX 1 /*Console on UART0 */ 34 35 /* 36 * Commands configuration 37 */ 38 #define CONFIG_CMD_PCI 39 40 /* NAND */ 41 #define CONFIG_SYS_NAND_ONFI_DETECTION 42 #define CONFIG_SYS_NAND_USE_FLASH_BBT 43 #define CONFIG_SYS_MAX_NAND_DEVICE 1 44 45 #define BBT_CUSTOM_SCAN 46 #define BBT_CUSTOM_SCAN_PAGE 0 47 #define BBT_CUSTOM_SCAN_POSITION 2048 48 49 /* SPI NOR flash default params, used by sf commands */ 50 #define CONFIG_SF_DEFAULT_BUS 1 51 #define CONFIG_SF_DEFAULT_SPEED 50000000 52 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 53 54 #define MTDIDS_DEFAULT "nand0=nand" 55 #define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)" 56 #define MTDPARTS_MTDOOPS "errlog" 57 58 /* Partition support */ 59 60 /* Additional FS support/configuration */ 61 62 /* USB/EHCI configuration */ 63 #define CONFIG_EHCI_IS_TDI 64 65 /* Environment in SPI NOR flash */ 66 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 67 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 68 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 69 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 70 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 71 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET 72 73 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 74 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 75 76 /* PCIe support */ 77 #ifndef CONFIG_SPL_BUILD 78 #define CONFIG_PCI_MVEBU 79 #define CONFIG_PCI_SCAN_SHOW 80 #endif 81 82 /* NAND */ 83 #define CONFIG_SYS_NAND_USE_FLASH_BBT 84 #define CONFIG_SYS_NAND_ONFI_DETECTION 85 #define CONFIG_CMD_UBI 86 #define CONFIG_CMD_UBIFS 87 #define CONFIG_LZO 88 #define CONFIG_MTD_DEVICE 89 #define CONFIG_CMD_MTDPARTS 90 91 #define CONFIG_SYS_MALLOC_LEN (4 << 20) 92 93 #include <asm/arch/config.h> 94 95 /* 96 * Other required minimal configurations 97 */ 98 #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 99 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ 100 101 #define CONFIG_SYS_ALT_MEMTEST 102 103 /* Keep device tree and initrd in low memory so the kernel can access them */ 104 #define CONFIG_EXTRA_ENV_SETTINGS \ 105 "fdt_high=0x10000000\0" \ 106 "initrd_high=0x10000000\0" 107 108 #define CONFIG_SYS_LOAD_ADDR 0x1000000 109 #define CONFIG_UBI_PART user 110 #define CONFIG_UBIFS_VOLUME user 111 112 /* SPL */ 113 114 /* Defines for SPL */ 115 #define CONFIG_SPL_SIZE (140 << 10) 116 #define CONFIG_SPL_TEXT_BASE 0x40000030 117 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) 118 119 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) 120 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 121 122 #ifdef CONFIG_SPL_BUILD 123 #define CONFIG_SYS_MALLOC_SIMPLE 124 #endif 125 126 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 127 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 128 129 /* SPL related SPI defines */ 130 #define CONFIG_SPL_SPI_LOAD 131 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 132 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 133 134 #endif /* _CONFIG_X530_H */ 135