1 /* 2 * WORK Microwave work_92105 board configuration file 3 * 4 * (C) Copyright 2014 DENX Software Engineering GmbH 5 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_WORK_92105_H__ 11 #define __CONFIG_WORK_92105_H__ 12 13 /* SoC and board defines */ 14 #include <linux/sizes.h> 15 #include <asm/arch/cpu.h> 16 17 /* 18 * Define work_92105 machine type by hand -- done only for compatibility 19 * with original board code 20 */ 21 #define CONFIG_MACH_TYPE 736 22 23 #define CONFIG_SYS_ICACHE_OFF 24 #define CONFIG_SYS_DCACHE_OFF 25 #if !defined(CONFIG_SPL_BUILD) 26 #define CONFIG_SKIP_LOWLEVEL_INIT 27 #endif 28 #define CONFIG_BOARD_EARLY_INIT_R 29 30 /* generate LPC32XX-specific SPL image */ 31 #define CONFIG_LPC32XX_SPL 32 33 /* 34 * Memory configurations 35 */ 36 #define CONFIG_NR_DRAM_BANKS 1 37 #define CONFIG_SYS_MALLOC_LEN SZ_1M 38 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE 39 #define CONFIG_SYS_SDRAM_SIZE SZ_128M 40 #define CONFIG_SYS_TEXT_BASE 0x80100000 41 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) 42 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) 43 44 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) 45 46 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ 47 - GENERATED_GBL_DATA_SIZE) 48 49 /* 50 * Serial Driver 51 */ 52 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ 53 #define CONFIG_BAUDRATE 115200 54 55 /* 56 * Ethernet Driver 57 */ 58 59 #define CONFIG_PHY_SMSC 60 #define CONFIG_LPC32XX_ETH 61 #define CONFIG_PHYLIB 62 #define CONFIG_PHY_ADDR 0 63 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 64 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ 65 66 /* 67 * I2C driver 68 */ 69 70 #define CONFIG_SYS_I2C_LPC32XX 71 #define CONFIG_SYS_I2C 72 #define CONFIG_SYS_I2C_SPEED 350000 73 74 /* 75 * I2C EEPROM 76 */ 77 78 #define CONFIG_CMD_EEPROM 79 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 80 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 81 82 /* 83 * I2C RTC 84 */ 85 86 #define CONFIG_CMD_DATE 87 #define CONFIG_RTC_DS1374 88 89 /* 90 * I2C Temperature Sensor (DTT) 91 */ 92 93 #define CONFIG_CMD_DTT 94 #define CONFIG_DTT_SENSORS { 0, 1 } 95 #define CONFIG_DTT_DS620 96 97 /* 98 * U-Boot General Configurations 99 */ 100 #define CONFIG_SYS_LONGHELP 101 #define CONFIG_SYS_CBSIZE 1024 102 #define CONFIG_SYS_PBSIZE \ 103 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 104 #define CONFIG_SYS_MAXARGS 16 105 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 106 107 #define CONFIG_AUTO_COMPLETE 108 #define CONFIG_CMDLINE_EDITING 109 110 /* 111 * NAND chip timings for FIXME: which one? 112 */ 113 114 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 115 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 116 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 117 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 118 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 119 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 120 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 121 122 /* 123 * NAND 124 */ 125 126 /* driver configuration */ 127 #define CONFIG_SYS_NAND_SELF_INIT 128 #define CONFIG_SYS_MAX_NAND_DEVICE 1 129 #define CONFIG_SYS_MAX_NAND_CHIPS 1 130 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE 131 #define CONFIG_NAND_LPC32XX_MLC 132 133 #define CONFIG_CMD_NAND 134 135 /* 136 * GPIO 137 */ 138 139 #define CONFIG_LPC32XX_GPIO 140 141 /* 142 * SSP/SPI/DISPLAY 143 */ 144 145 #define CONFIG_LPC32XX_SSP 146 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 147 #define CONFIG_CMD_MAX6957 148 #define CONFIG_CMD_HD44760 149 /* 150 * Environment 151 */ 152 153 #define CONFIG_ENV_IS_IN_NAND 1 154 #define CONFIG_ENV_SIZE 0x00020000 155 #define CONFIG_ENV_OFFSET 0x00100000 156 #define CONFIG_ENV_OFFSET_REDUND 0x00120000 157 #define CONFIG_ENV_ADDR 0x80000100 158 159 /* 160 * Boot Linux 161 */ 162 #define CONFIG_CMDLINE_TAG 163 #define CONFIG_SETUP_MEMORY_TAGS 164 #define CONFIG_INITRD_TAG 165 166 #define CONFIG_BOOTFILE "uImage" 167 #define CONFIG_BOOTARGS "console=ttyS2,115200n8" 168 #define CONFIG_LOADADDR 0x80008000 169 170 /* 171 * SPL 172 */ 173 174 /* SPL will be executed at offset 0 */ 175 #define CONFIG_SPL_TEXT_BASE 0x00000000 176 /* SPL will use SRAM as stack */ 177 #define CONFIG_SPL_STACK 0x0000FFF8 178 #define CONFIG_SPL_BOARD_INIT 179 /* Use the framework and generic lib */ 180 #define CONFIG_SPL_FRAMEWORK 181 /* SPL will use serial */ 182 /* SPL will load U-Boot from NAND offset 0x40000 */ 183 #define CONFIG_SPL_NAND_DRIVERS 184 #define CONFIG_SPL_NAND_BASE 185 #define CONFIG_SPL_NAND_BOOT 186 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 187 #define CONFIG_SPL_PAD_TO 0x20000 188 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ 189 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ 190 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 191 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 192 193 /* 194 * Include SoC specific configuration 195 */ 196 #include <asm/arch/config.h> 197 198 #endif /* __CONFIG_WORK_92105_H__*/ 199