1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * WORK Microwave work_92105 board configuration file 4 * 5 * (C) Copyright 2014 DENX Software Engineering GmbH 6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 7 */ 8 9 #ifndef __CONFIG_WORK_92105_H__ 10 #define __CONFIG_WORK_92105_H__ 11 12 /* SoC and board defines */ 13 #include <linux/sizes.h> 14 #include <asm/arch/cpu.h> 15 16 /* 17 * Define work_92105 machine type by hand -- done only for compatibility 18 * with original board code 19 */ 20 #define CONFIG_MACH_TYPE 736 21 22 #define CONFIG_SYS_ICACHE_OFF 23 #define CONFIG_SYS_DCACHE_OFF 24 #if !defined(CONFIG_SPL_BUILD) 25 #define CONFIG_SKIP_LOWLEVEL_INIT 26 #endif 27 28 /* 29 * Memory configurations 30 */ 31 #define CONFIG_SYS_MALLOC_LEN SZ_1M 32 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE 33 #define CONFIG_SYS_SDRAM_SIZE SZ_128M 34 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) 35 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) 36 37 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) 38 39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ 40 - GENERATED_GBL_DATA_SIZE) 41 42 /* 43 * Serial Driver 44 */ 45 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ 46 47 /* 48 * Ethernet Driver 49 */ 50 51 #define CONFIG_PHY_SMSC 52 #define CONFIG_LPC32XX_ETH 53 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 54 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ 55 56 /* 57 * I2C driver 58 */ 59 60 #define CONFIG_SYS_I2C_LPC32XX 61 #define CONFIG_SYS_I2C 62 #define CONFIG_SYS_I2C_SPEED 350000 63 64 /* 65 * I2C EEPROM 66 */ 67 68 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 69 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 70 71 /* 72 * I2C RTC 73 */ 74 75 #define CONFIG_RTC_DS1374 76 77 /* 78 * U-Boot General Configurations 79 */ 80 #define CONFIG_SYS_CBSIZE 1024 81 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 82 83 /* 84 * NAND chip timings for FIXME: which one? 85 */ 86 87 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 88 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 89 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 90 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 91 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 92 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 93 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 94 95 /* 96 * NAND 97 */ 98 99 /* driver configuration */ 100 #define CONFIG_SYS_NAND_SELF_INIT 101 #define CONFIG_SYS_MAX_NAND_DEVICE 1 102 #define CONFIG_SYS_MAX_NAND_CHIPS 1 103 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE 104 #define CONFIG_NAND_LPC32XX_MLC 105 106 /* 107 * GPIO 108 */ 109 110 #define CONFIG_LPC32XX_GPIO 111 112 /* 113 * SSP/SPI/DISPLAY 114 */ 115 116 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000 117 /* 118 * Environment 119 */ 120 121 #define CONFIG_ENV_SIZE 0x00020000 122 #define CONFIG_ENV_OFFSET 0x00100000 123 #define CONFIG_ENV_OFFSET_REDUND 0x00120000 124 #define CONFIG_ENV_ADDR 0x80000100 125 126 /* 127 * Boot Linux 128 */ 129 #define CONFIG_CMDLINE_TAG 130 #define CONFIG_SETUP_MEMORY_TAGS 131 #define CONFIG_INITRD_TAG 132 133 #define CONFIG_BOOTFILE "uImage" 134 #define CONFIG_LOADADDR 0x80008000 135 136 /* 137 * SPL 138 */ 139 140 /* SPL will be executed at offset 0 */ 141 #define CONFIG_SPL_TEXT_BASE 0x00000000 142 /* SPL will use SRAM as stack */ 143 #define CONFIG_SPL_STACK 0x0000FFF8 144 /* Use the framework and generic lib */ 145 /* SPL will use serial */ 146 /* SPL will load U-Boot from NAND offset 0x40000 */ 147 #define CONFIG_SPL_NAND_DRIVERS 148 #define CONFIG_SPL_NAND_BASE 149 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 150 #define CONFIG_SPL_PAD_TO 0x20000 151 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ 152 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ 153 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 154 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 155 156 /* 157 * Include SoC specific configuration 158 */ 159 #include <asm/arch/config.h> 160 161 #endif /* __CONFIG_WORK_92105_H__*/ 162