1 /* 2 * Configuation settings for the WB50N CPU Module. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <asm/hardware.h> 11 12 /* ARM asynchronous clock */ 13 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 14 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 15 16 #define CONFIG_ARCH_CPU_INIT 17 18 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 19 #define CONFIG_SETUP_MEMORY_TAGS 20 #define CONFIG_INITRD_TAG 21 22 #ifndef CONFIG_SPL_BUILD 23 #define CONFIG_SKIP_LOWLEVEL_INIT 24 #endif 25 26 #define CONFIG_IMAGE_FORMAT_LEGACY 27 28 /* general purpose I/O */ 29 #define CONFIG_AT91_GPIO 30 31 /* serial console */ 32 #define CONFIG_ATMEL_USART 33 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 34 #define CONFIG_USART_ID ATMEL_ID_DBGU 35 36 /* 37 * BOOTP options 38 */ 39 #define CONFIG_BOOTP_BOOTFILESIZE 40 41 /* SDRAM */ 42 #define CONFIG_NR_DRAM_BANKS 1 43 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 44 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 45 46 #ifdef CONFIG_SPL_BUILD 47 #define CONFIG_SYS_INIT_SP_ADDR 0x310000 48 #else 49 #define CONFIG_SYS_INIT_SP_ADDR \ 50 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 51 #endif 52 53 #define CONFIG_SYS_MEMTEST_START 0x21000000 54 #define CONFIG_SYS_MEMTEST_END 0x22000000 55 56 /* NAND flash */ 57 #define CONFIG_NAND_ATMEL 58 #define CONFIG_SYS_MAX_NAND_DEVICE 1 59 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 60 /* our ALE is AD21 */ 61 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 62 /* our CLE is AD22 */ 63 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 64 #define CONFIG_SYS_NAND_ONFI_DETECTION 65 /* PMECC & PMERRLOC */ 66 #define CONFIG_ATMEL_NAND_HWECC 67 #define CONFIG_ATMEL_NAND_HW_PMECC 68 #define CONFIG_PMECC_CAP 8 69 #define CONFIG_PMECC_SECTOR_SIZE 512 70 71 /* Ethernet Hardware */ 72 #define CONFIG_MACB 73 #define CONFIG_RMII 74 #define CONFIG_NET_RETRY_COUNT 20 75 #define CONFIG_MACB_SEARCH_PHY 76 #define CONFIG_RGMII 77 #define CONFIG_ETHADDR C0:EE:40:00:00:00 78 #define CONFIG_ENV_OVERWRITE 1 79 80 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 81 82 #define CONFIG_EXTRA_ENV_SETTINGS \ 83 "autoload=no\0" \ 84 "autostart=no\0" 85 86 /* bootstrap + u-boot + env in nandflash */ 87 #define CONFIG_ENV_OFFSET 0xA0000 88 #define CONFIG_ENV_OFFSET_REDUND 0xC0000 89 #define CONFIG_ENV_SIZE 0x20000 90 #define CONFIG_BOOTCOMMAND \ 91 "nand read 0x22000000 0x000e0000 0x500000; " \ 92 "bootm" 93 94 #define CONFIG_BOOTARGS \ 95 "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" 96 97 #define CONFIG_BAUDRATE 115200 98 99 #define CONFIG_SYS_CBSIZE 1024 100 #define CONFIG_SYS_MAXARGS 16 101 #define CONFIG_SYS_PBSIZE \ 102 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 103 104 /* Size of malloc() pool */ 105 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 106 107 /* SPL */ 108 #define CONFIG_SPL_TEXT_BASE 0x300000 109 #define CONFIG_SPL_MAX_SIZE 0x10000 110 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 111 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 112 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 113 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 114 115 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 116 117 #define CONFIG_SPL_NAND_DRIVERS 118 #define CONFIG_SPL_NAND_BASE 119 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 120 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 121 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 122 #define CONFIG_SYS_NAND_PAGE_COUNT 64 123 #define CONFIG_SYS_NAND_OOBSIZE 64 124 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 125 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 126 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 127 128 #endif 129