1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the WB50N CPU Module. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #include <asm/hardware.h> 10 11 /* ARM asynchronous clock */ 12 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 13 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 14 15 #define CONFIG_ARCH_CPU_INIT 16 17 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 18 #define CONFIG_SETUP_MEMORY_TAGS 19 #define CONFIG_INITRD_TAG 20 21 #ifndef CONFIG_SPL_BUILD 22 #define CONFIG_SKIP_LOWLEVEL_INIT 23 #endif 24 25 /* general purpose I/O */ 26 #define CONFIG_AT91_GPIO 27 28 /* serial console */ 29 #define CONFIG_ATMEL_USART 30 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 31 #define CONFIG_USART_ID ATMEL_ID_DBGU 32 33 /* 34 * BOOTP options 35 */ 36 #define CONFIG_BOOTP_BOOTFILESIZE 37 38 /* SDRAM */ 39 #define CONFIG_NR_DRAM_BANKS 1 40 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 41 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 42 43 #ifdef CONFIG_SPL_BUILD 44 #define CONFIG_SYS_INIT_SP_ADDR 0x310000 45 #else 46 #define CONFIG_SYS_INIT_SP_ADDR \ 47 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 48 #endif 49 50 #define CONFIG_SYS_MEMTEST_START 0x21000000 51 #define CONFIG_SYS_MEMTEST_END 0x22000000 52 53 /* NAND flash */ 54 #define CONFIG_SYS_MAX_NAND_DEVICE 1 55 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 56 /* our ALE is AD21 */ 57 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 58 /* our CLE is AD22 */ 59 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 60 #define CONFIG_SYS_NAND_ONFI_DETECTION 61 /* PMECC & PMERRLOC */ 62 #define CONFIG_ATMEL_NAND_HWECC 63 #define CONFIG_ATMEL_NAND_HW_PMECC 64 #define CONFIG_PMECC_CAP 8 65 #define CONFIG_PMECC_SECTOR_SIZE 512 66 67 /* Ethernet Hardware */ 68 #define CONFIG_MACB 69 #define CONFIG_RMII 70 #define CONFIG_NET_RETRY_COUNT 20 71 #define CONFIG_MACB_SEARCH_PHY 72 #define CONFIG_RGMII 73 #define CONFIG_ETHADDR C0:EE:40:00:00:00 74 #define CONFIG_ENV_OVERWRITE 1 75 76 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 77 78 #define CONFIG_EXTRA_ENV_SETTINGS \ 79 "autoload=no\0" \ 80 "autostart=no\0" 81 82 /* bootstrap + u-boot + env in nandflash */ 83 #define CONFIG_ENV_OFFSET 0xA0000 84 #define CONFIG_ENV_OFFSET_REDUND 0xC0000 85 #define CONFIG_ENV_SIZE 0x20000 86 #define CONFIG_BOOTCOMMAND \ 87 "nand read 0x22000000 0x000e0000 0x500000; " \ 88 "bootm" 89 90 #define CONFIG_BOOTARGS \ 91 "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" 92 93 #define CONFIG_BAUDRATE 115200 94 95 #define CONFIG_SYS_CBSIZE 1024 96 #define CONFIG_SYS_MAXARGS 16 97 #define CONFIG_SYS_PBSIZE \ 98 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 99 100 /* Size of malloc() pool */ 101 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 102 103 /* SPL */ 104 #define CONFIG_SPL_TEXT_BASE 0x300000 105 #define CONFIG_SPL_MAX_SIZE 0x10000 106 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 107 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 108 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 109 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 110 111 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 112 113 #define CONFIG_SPL_NAND_DRIVERS 114 #define CONFIG_SPL_NAND_BASE 115 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 116 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 117 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 118 #define CONFIG_SYS_NAND_PAGE_COUNT 64 119 #define CONFIG_SYS_NAND_OOBSIZE 64 120 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 121 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 122 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 123 124 #endif 125