1 /* 2 * Configuation settings for the WB50N CPU Module. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <asm/hardware.h> 11 12 #define CONFIG_SYS_TEXT_BASE 0x23f00000 13 14 /* ARM asynchronous clock */ 15 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 16 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 17 18 #define CONFIG_ARCH_CPU_INIT 19 20 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 21 #define CONFIG_SETUP_MEMORY_TAGS 22 #define CONFIG_INITRD_TAG 23 24 #ifndef CONFIG_SPL_BUILD 25 #define CONFIG_SKIP_LOWLEVEL_INIT 26 #endif 27 28 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 29 #define CONFIG_IMAGE_FORMAT_LEGACY 30 31 /* general purpose I/O */ 32 #define CONFIG_AT91_GPIO 33 34 /* serial console */ 35 #define CONFIG_ATMEL_USART 36 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 37 #define CONFIG_USART_ID ATMEL_ID_DBGU 38 39 /* 40 * BOOTP options 41 */ 42 #define CONFIG_BOOTP_BOOTFILESIZE 43 #define CONFIG_BOOTP_BOOTPATH 44 #define CONFIG_BOOTP_GATEWAY 45 #define CONFIG_BOOTP_HOSTNAME 46 47 /* SDRAM */ 48 #define CONFIG_NR_DRAM_BANKS 1 49 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 50 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 51 52 #ifdef CONFIG_SPL_BUILD 53 #define CONFIG_SYS_INIT_SP_ADDR 0x310000 54 #else 55 #define CONFIG_SYS_INIT_SP_ADDR \ 56 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 57 #endif 58 59 #define CONFIG_SYS_MEMTEST_START 0x21000000 60 #define CONFIG_SYS_MEMTEST_END 0x22000000 61 #define CONFIG_SYS_ALT_MEMTEST 62 63 /* NAND flash */ 64 #define CONFIG_NAND_ATMEL 65 #define CONFIG_SYS_MAX_NAND_DEVICE 1 66 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 67 /* our ALE is AD21 */ 68 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 69 /* our CLE is AD22 */ 70 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 71 #define CONFIG_SYS_NAND_ONFI_DETECTION 72 /* PMECC & PMERRLOC */ 73 #define CONFIG_ATMEL_NAND_HWECC 74 #define CONFIG_ATMEL_NAND_HW_PMECC 75 #define CONFIG_PMECC_CAP 8 76 #define CONFIG_PMECC_SECTOR_SIZE 512 77 78 /* Ethernet Hardware */ 79 #define CONFIG_MACB 80 #define CONFIG_RMII 81 #define CONFIG_NET_RETRY_COUNT 20 82 #define CONFIG_MACB_SEARCH_PHY 83 #define CONFIG_RGMII 84 #define CONFIG_ETHADDR C0:EE:40:00:00:00 85 #define CONFIG_ENV_OVERWRITE 1 86 87 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 88 89 #define CONFIG_EXTRA_ENV_SETTINGS \ 90 "autoload=no\0" \ 91 "autostart=no\0" 92 93 /* bootstrap + u-boot + env in nandflash */ 94 #define CONFIG_ENV_OFFSET 0xA0000 95 #define CONFIG_ENV_OFFSET_REDUND 0xC0000 96 #define CONFIG_ENV_SIZE 0x20000 97 #define CONFIG_BOOTCOMMAND \ 98 "nand read 0x22000000 0x000e0000 0x500000; " \ 99 "bootm" 100 101 #define CONFIG_BOOTARGS \ 102 "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" 103 104 #define CONFIG_BAUDRATE 115200 105 106 #define CONFIG_SYS_CBSIZE 1024 107 #define CONFIG_SYS_MAXARGS 16 108 #define CONFIG_SYS_PBSIZE \ 109 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 110 #define CONFIG_SYS_LONGHELP 111 #define CONFIG_CMDLINE_EDITING 112 #define CONFIG_AUTO_COMPLETE 113 114 /* Size of malloc() pool */ 115 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 116 117 /* SPL */ 118 #define CONFIG_SPL_FRAMEWORK 119 #define CONFIG_SPL_TEXT_BASE 0x300000 120 #define CONFIG_SPL_MAX_SIZE 0x10000 121 #define CONFIG_SPL_BSS_START_ADDR 0x20000000 122 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 123 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 124 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 125 126 #define CONFIG_SYS_MONITOR_LEN (512 << 10) 127 128 #define CONFIG_SPL_NAND_DRIVERS 129 #define CONFIG_SPL_NAND_BASE 130 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 131 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 132 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 133 #define CONFIG_SYS_NAND_PAGE_COUNT 64 134 #define CONFIG_SYS_NAND_OOBSIZE 64 135 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 136 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 137 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 138 139 #endif 140