1 /* 2 * esd vme8349 U-Boot configuration file 3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4 * 5 * (C) Copyright 2006 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * reinhard.arlt@esd-electronics.de 9 * Based on the MPC8349EMDS config. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 /* 31 * vme8349 board configuration file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* 38 * Top level Makefile configuration choices 39 */ 40 #ifdef CONFIG_MK_caddy2 41 #define VME_CADDY2 42 #endif 43 44 /* 45 * High Level Configuration Options 46 */ 47 #define CONFIG_E300 1 /* E300 Family */ 48 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 49 #define CONFIG_MPC834x 1 /* MPC834x family */ 50 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 51 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 52 53 #define CONFIG_MISC_INIT_R 54 55 #define CONFIG_PCI 56 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 57 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 58 59 #define PCI_66M 60 #ifdef PCI_66M 61 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 62 #else 63 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 64 #endif 65 66 #ifndef CONFIG_SYS_CLK_FREQ 67 #ifdef PCI_66M 68 #define CONFIG_SYS_CLK_FREQ 66000000 69 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 70 #else 71 #define CONFIG_SYS_CLK_FREQ 33000000 72 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 73 #endif 74 #endif 75 76 #define CONFIG_SYS_IMMR 0xE0000000 77 78 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 79 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 80 #define CONFIG_SYS_MEMTEST_END 0x00100000 81 82 /* 83 * DDR Setup 84 */ 85 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 86 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 87 #define CONFIG_SPD_EEPROM 88 #define SPD_EEPROM_ADDRESS 0x54 89 #define CONFIG_SYS_READ_SPD vme8349_read_spd 90 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 91 92 /* 93 * 32-bit data path mode. 94 * 95 * Please note that using this mode for devices with the real density of 64-bit 96 * effectively reduces the amount of available memory due to the effect of 97 * wrapping around while translating address to row/columns, for example in the 98 * 256MB module the upper 128MB get aliased with contents of the lower 99 * 128MB); normally this define should be used for devices with real 32-bit 100 * data path. 101 */ 102 #undef CONFIG_DDR_32BIT 103 104 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 106 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 107 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 108 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 109 #define CONFIG_DDR_2T_TIMING 110 #define CONFIG_SYS_DDRCDR 0x80080001 111 112 /* 113 * FLASH on the Local Bus 114 */ 115 #define CONFIG_SYS_FLASH_CFI 116 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 117 #ifdef VME_CADDY2 118 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 119 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 120 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 121 (2 << BR_PS_SHIFT) | /* 16bit */ \ 122 BR_V) /* valid */ 123 124 #define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */ 125 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 126 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */ 127 #else 128 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 129 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 130 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 131 (2 << BR_PS_SHIFT) | /* 16bit */ \ 132 BR_V) /* valid */ 133 134 #define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */ 135 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 136 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */ 137 #endif 138 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 139 140 #define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801) 141 #define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200) 142 #define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000 143 #define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011) 144 145 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 146 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 147 148 #undef CONFIG_SYS_FLASH_CHECKSUM 149 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 150 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 151 152 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 153 154 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 155 #define CONFIG_SYS_RAMBOOT 156 #else 157 #undef CONFIG_SYS_RAMBOOT 158 #endif 159 160 #define CONFIG_SYS_INIT_RAM_LOCK 1 161 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 162 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* size */ 163 164 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* size init data */ 165 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ 166 CONFIG_SYS_GBL_DATA_SIZE) 167 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 168 169 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 170 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Malloc size */ 171 172 /* 173 * Local Bus LCRR and LBCR regs 174 * LCRR: no DLL bypass, Clock divider is 4 175 * External Local Bus rate is 176 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 177 */ 178 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 179 #define CONFIG_SYS_LBC_LBCR 0x00000000 180 181 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 182 183 /* 184 * Serial Port 185 */ 186 #define CONFIG_CONS_INDEX 1 187 #undef CONFIG_SERIAL_SOFTWARE_FIFO 188 #define CONFIG_SYS_NS16550 189 #define CONFIG_SYS_NS16550_SERIAL 190 #define CONFIG_SYS_NS16550_REG_SIZE 1 191 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 192 193 #define CONFIG_SYS_BAUDRATE_TABLE \ 194 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 195 196 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 197 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 198 199 #define CONFIG_CMDLINE_EDITING /* add command line history */ 200 /* Use the HUSH parser */ 201 #define CONFIG_SYS_HUSH_PARSER 202 #ifdef CONFIG_SYS_HUSH_PARSER 203 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 204 #endif 205 206 /* pass open firmware flat tree */ 207 #define CONFIG_OF_LIBFDT 208 #define CONFIG_OF_BOARD_SETUP 209 #define CONFIG_OF_STDOUT_VIA_ALIAS 210 211 /* I2C */ 212 #define CONFIG_I2C_MULTI_BUS 213 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 214 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 215 #define CONFIG_FSL_I2C 216 #define CONFIG_I2C_CMD_TREE 217 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 218 #define CONFIG_SYS_I2C_SLAVE 0x7F 219 #define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}} /* Don't probe these addrs */ 220 #define CONFIG_SYS_I2C1_OFFSET 0x3000 221 #define CONFIG_SYS_I2C2_OFFSET 0x3100 222 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET 223 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 224 225 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 226 227 /* TSEC */ 228 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 229 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 230 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 231 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 232 233 /* 234 * General PCI 235 * Addresses are mapped 1-1. 236 */ 237 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 238 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 239 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 240 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 241 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 242 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 243 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 244 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 245 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 246 247 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 248 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 249 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 250 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 251 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 252 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 253 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 254 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 255 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 256 257 #if defined(CONFIG_PCI) 258 259 #define PCI_64BIT 260 #define PCI_ONE_PCI1 261 #if defined(PCI_64BIT) 262 #undef PCI_ALL_PCI1 263 #undef PCI_TWO_PCI1 264 #undef PCI_ONE_PCI1 265 #endif 266 267 #ifndef VME_CADDY2 268 #define CONFIG_NET_MULTI 269 #endif 270 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 271 272 #undef CONFIG_EEPRO100 273 #undef CONFIG_TULIP 274 275 #if !defined(CONFIG_PCI_PNP) 276 #define PCI_ENET0_IOADDR 0xFIXME 277 #define PCI_ENET0_MEMADDR 0xFIXME 278 #define PCI_IDSEL_NUMBER 0xFIXME 279 #endif 280 281 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 282 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 283 284 #endif /* CONFIG_PCI */ 285 286 /* 287 * TSEC configuration 288 */ 289 #ifdef VME_CADDY2 290 #define CONFIG_E1000 291 #else 292 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 293 #endif 294 295 #if defined(CONFIG_TSEC_ENET) 296 #ifndef CONFIG_NET_MULTI 297 #define CONFIG_NET_MULTI 298 #endif 299 300 #define CONFIG_GMII /* MII PHY management */ 301 #define CONFIG_TSEC1 302 #define CONFIG_TSEC1_NAME "TSEC0" 303 #define CONFIG_TSEC2 304 #define CONFIG_TSEC2_NAME "TSEC1" 305 #define CONFIG_PHY_M88E1111 306 #define TSEC1_PHY_ADDR 0x08 307 #define TSEC2_PHY_ADDR 0x10 308 #define TSEC1_PHYIDX 0 309 #define TSEC2_PHYIDX 0 310 #define TSEC1_FLAGS TSEC_GIGABIT 311 #define TSEC2_FLAGS TSEC_GIGABIT 312 313 /* Options are: TSEC[0-1] */ 314 #define CONFIG_ETHPRIME "TSEC0" 315 316 #endif /* CONFIG_TSEC_ENET */ 317 318 #if defined(CONFIG_E1000) 319 #ifndef CONFIG_NET_MULTI 320 #define CONFIG_NET_MULTI 321 #endif 322 #endif 323 324 /* 325 * Environment 326 */ 327 #ifndef CONFIG_SYS_RAMBOOT 328 #define CONFIG_ENV_IS_IN_FLASH 329 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 330 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 331 #define CONFIG_ENV_SIZE 0x2000 332 333 /* Address and size of Redundant Environment Sector */ 334 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 335 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 336 337 #else 338 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 339 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 340 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 341 #define CONFIG_ENV_SIZE 0x2000 342 #endif 343 344 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 345 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 346 347 /* 348 * BOOTP options 349 */ 350 #define CONFIG_BOOTP_BOOTFILESIZE 351 #define CONFIG_BOOTP_BOOTPATH 352 #define CONFIG_BOOTP_GATEWAY 353 #define CONFIG_BOOTP_HOSTNAME 354 355 /* 356 * Command line configuration. 357 */ 358 #include <config_cmd_default.h> 359 360 #define CONFIG_CMD_I2C 361 #define CONFIG_CMD_MII 362 #define CONFIG_CMD_PING 363 #define CONFIG_CMD_DATE 364 #define CONFIG_SYS_RTC_BUS_NUM 0x01 365 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 366 #define CONFIG_RTC_RX8025 367 #define CONFIG_CMD_TSI148 368 369 #if defined(CONFIG_PCI) 370 #define CONFIG_CMD_PCI 371 #endif 372 373 #if defined(CONFIG_SYS_RAMBOOT) 374 #undef CONFIG_CMD_ENV 375 #undef CONFIG_CMD_LOADS 376 #endif 377 378 #define CONFIG_CMD_ELF 379 /* Pass Ethernet MAC to VxWorks */ 380 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 381 382 #undef CONFIG_WATCHDOG /* watchdog disabled */ 383 384 /* 385 * Miscellaneous configurable options 386 */ 387 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 388 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 389 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 390 391 #if defined(CONFIG_CMD_KGDB) 392 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 393 #else 394 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 395 #endif 396 397 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 398 #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ 399 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ 400 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 401 402 /* 403 * For booting Linux, the board info and command line data 404 * have to be in the first 8 MB of memory, since this is 405 * the maximum mapped by the Linux kernel during initialization. 406 */ 407 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init Memory map for Linux*/ 408 409 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 410 411 #define CONFIG_SYS_HRCW_LOW (\ 412 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 413 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 414 HRCWL_CSB_TO_CLKIN |\ 415 HRCWL_VCO_1X2 |\ 416 HRCWL_CORE_TO_CSB_2X1) 417 418 #if defined(PCI_64BIT) 419 #define CONFIG_SYS_HRCW_HIGH (\ 420 HRCWH_PCI_HOST |\ 421 HRCWH_64_BIT_PCI |\ 422 HRCWH_PCI1_ARBITER_ENABLE |\ 423 HRCWH_PCI2_ARBITER_DISABLE |\ 424 HRCWH_CORE_ENABLE |\ 425 HRCWH_FROM_0X00000100 |\ 426 HRCWH_BOOTSEQ_DISABLE |\ 427 HRCWH_SW_WATCHDOG_DISABLE |\ 428 HRCWH_ROM_LOC_LOCAL_16BIT |\ 429 HRCWH_TSEC1M_IN_GMII |\ 430 HRCWH_TSEC2M_IN_GMII) 431 #else 432 #define CONFIG_SYS_HRCW_HIGH (\ 433 HRCWH_PCI_HOST |\ 434 HRCWH_32_BIT_PCI |\ 435 HRCWH_PCI1_ARBITER_ENABLE |\ 436 HRCWH_PCI2_ARBITER_ENABLE |\ 437 HRCWH_CORE_ENABLE |\ 438 HRCWH_FROM_0X00000100 |\ 439 HRCWH_BOOTSEQ_DISABLE |\ 440 HRCWH_SW_WATCHDOG_DISABLE |\ 441 HRCWH_ROM_LOC_LOCAL_16BIT |\ 442 HRCWH_TSEC1M_IN_GMII |\ 443 HRCWH_TSEC2M_IN_GMII) 444 #endif 445 446 /* System IO Config */ 447 #define CONFIG_SYS_SICRH 0 448 #define CONFIG_SYS_SICRL SICRL_LDP_A 449 450 #define CONFIG_SYS_HID0_INIT 0x000000000 451 #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 452 453 #define CONFIG_SYS_HID2 HID2_HBE 454 455 #define CONFIG_SYS_GPIO1_PRELIM 456 #define CONFIG_SYS_GPIO1_DIR 0x00100000 457 #define CONFIG_SYS_GPIO1_DAT 0x00100000 458 459 #define CONFIG_SYS_GPIO2_PRELIM 460 #define CONFIG_SYS_GPIO2_DIR 0x78900000 461 #define CONFIG_SYS_GPIO2_DAT 0x70100000 462 463 #define CONFIG_HIGH_BATS /* High BATs supported */ 464 465 /* DDR @ 0x00000000 */ 466 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ 467 BATL_MEMCOHERENCE) 468 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 469 BATU_VS | BATU_VP) 470 471 /* PCI @ 0x80000000 */ 472 #ifdef CONFIG_PCI 473 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \ 474 BATL_MEMCOHERENCE) 475 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 476 BATU_VS | BATU_VP) 477 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \ 478 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 479 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 480 BATU_VS | BATU_VP) 481 #else 482 #define CONFIG_SYS_IBAT1L (0) 483 #define CONFIG_SYS_IBAT1U (0) 484 #define CONFIG_SYS_IBAT2L (0) 485 #define CONFIG_SYS_IBAT2U (0) 486 #endif 487 488 #ifdef CONFIG_MPC83XX_PCI2 489 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \ 490 BATL_MEMCOHERENCE) 491 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 492 BATU_VS | BATU_VP) 493 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \ 494 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 495 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 496 BATU_VS | BATU_VP) 497 #else 498 #define CONFIG_SYS_IBAT3L (0) 499 #define CONFIG_SYS_IBAT3U (0) 500 #define CONFIG_SYS_IBAT4L (0) 501 #define CONFIG_SYS_IBAT4U (0) 502 #endif 503 504 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 505 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 506 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 507 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 508 BATU_VS | BATU_VP) 509 510 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 511 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 512 513 #if (CONFIG_SYS_DDR_SIZE == 512) 514 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 515 BATL_PP_10 | BATL_MEMCOHERENCE) 516 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 517 BATU_BL_256M | BATU_VS | BATU_VP) 518 #else 519 #define CONFIG_SYS_IBAT7L (0) 520 #define CONFIG_SYS_IBAT7U (0) 521 #endif 522 523 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 524 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 525 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 526 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 527 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 528 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 529 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 530 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 531 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 532 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 533 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 534 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 535 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 536 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 537 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 538 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 539 540 /* 541 * Internal Definitions 542 * 543 * Boot Flags 544 */ 545 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 546 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 547 548 #if defined(CONFIG_CMD_KGDB) 549 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 550 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 551 #endif 552 553 /* 554 * Environment Configuration 555 */ 556 #define CONFIG_ENV_OVERWRITE 557 558 #if defined(CONFIG_TSEC_ENET) 559 #define CONFIG_HAS_ETH0 560 #define CONFIG_HAS_ETH1 561 #endif 562 563 #define CONFIG_HOSTNAME VME8349 564 #define CONFIG_ROOTPATH /tftpboot/rootfs 565 #define CONFIG_BOOTFILE uImage 566 567 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 568 569 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 570 #undef CONFIG_BOOTARGS /* boot command will set bootargs */ 571 572 #define CONFIG_BAUDRATE 9600 573 574 #define CONFIG_EXTRA_ENV_SETTINGS \ 575 "netdev=eth0\0" \ 576 "hostname=vme8349\0" \ 577 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 578 "nfsroot=${serverip}:${rootpath}\0" \ 579 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 580 "addip=setenv bootargs ${bootargs} " \ 581 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 582 ":${hostname}:${netdev}:off panic=1\0" \ 583 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 584 "flash_nfs=run nfsargs addip addtty;" \ 585 "bootm ${kernel_addr}\0" \ 586 "flash_self=run ramargs addip addtty;" \ 587 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 588 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 589 "bootm\0" \ 590 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 591 "update=protect off fff00000 fff3ffff; " \ 592 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 593 "upd=run load update\0" \ 594 "fdtaddr=780000\0" \ 595 "fdtfile=vme8349.dtb\0" \ 596 "" 597 598 #define CONFIG_NFSBOOTCOMMAND \ 599 "setenv bootargs root=/dev/nfs rw " \ 600 "nfsroot=$serverip:$rootpath " \ 601 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 602 "console=$consoledev,$baudrate $othbootargs;" \ 603 "tftp $loadaddr $bootfile;" \ 604 "tftp $fdtaddr $fdtfile;" \ 605 "bootm $loadaddr - $fdtaddr" 606 607 #define CONFIG_RAMBOOTCOMMAND \ 608 "setenv bootargs root=/dev/ram rw " \ 609 "console=$consoledev,$baudrate $othbootargs;" \ 610 "tftp $ramdiskaddr $ramdiskfile;" \ 611 "tftp $loadaddr $bootfile;" \ 612 "tftp $fdtaddr $fdtfile;" \ 613 "bootm $loadaddr $ramdiskaddr $fdtaddr" 614 615 #define CONFIG_BOOTCOMMAND "run flash_self" 616 617 #ifndef __ASSEMBLY__ 618 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 619 unsigned char *buffer, int len); 620 #endif 621 622 #endif /* __CONFIG_H */ 623