1 /* 2 * esd vme8349 U-Boot configuration file 3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4 * 5 * (C) Copyright 2006-2010 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * reinhard.arlt@esd-electronics.de 9 * Based on the MPC8349EMDS config. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 /* 15 * vme8349 board configuration file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* 22 * Top level Makefile configuration choices 23 */ 24 #ifdef CONFIG_CADDY2 25 #define VME_CADDY2 26 #endif 27 28 /* 29 * High Level Configuration Options 30 */ 31 #define CONFIG_E300 1 /* E300 Family */ 32 #define CONFIG_MPC834x 1 /* MPC834x family */ 33 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 34 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 35 36 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 37 38 #define CONFIG_MISC_INIT_R 39 40 #define CONFIG_PCI 41 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 42 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 43 44 #define CONFIG_PCI_66M 45 #ifdef CONFIG_PCI_66M 46 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 47 #else 48 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 49 #endif 50 51 #ifndef CONFIG_SYS_CLK_FREQ 52 #ifdef CONFIG_PCI_66M 53 #define CONFIG_SYS_CLK_FREQ 66000000 54 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 55 #else 56 #define CONFIG_SYS_CLK_FREQ 33000000 57 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 58 #endif 59 #endif 60 61 #define CONFIG_SYS_IMMR 0xE0000000 62 63 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 64 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 65 #define CONFIG_SYS_MEMTEST_END 0x00100000 66 67 /* 68 * DDR Setup 69 */ 70 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 71 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 72 #define CONFIG_SPD_EEPROM 73 #define SPD_EEPROM_ADDRESS 0x54 74 #define CONFIG_SYS_READ_SPD vme8349_read_spd 75 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 76 77 /* 78 * 32-bit data path mode. 79 * 80 * Please note that using this mode for devices with the real density of 64-bit 81 * effectively reduces the amount of available memory due to the effect of 82 * wrapping around while translating address to row/columns, for example in the 83 * 256MB module the upper 128MB get aliased with contents of the lower 84 * 128MB); normally this define should be used for devices with real 32-bit 85 * data path. 86 */ 87 #undef CONFIG_DDR_32BIT 88 89 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 90 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 91 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 92 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 93 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 94 #define CONFIG_DDR_2T_TIMING 95 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 96 | DDRCDR_ODT \ 97 | DDRCDR_Q_DRN) 98 /* 0x80080001 */ 99 100 /* 101 * FLASH on the Local Bus 102 */ 103 #define CONFIG_SYS_FLASH_CFI 104 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 105 #ifdef VME_CADDY2 106 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 107 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 108 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 109 BR_PS_16 | /* 16bit */ \ 110 BR_MS_GPCM | /* MSEL = GPCM */ \ 111 BR_V) /* valid */ 112 113 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 114 | OR_GPCM_XAM \ 115 | OR_GPCM_CSNT \ 116 | OR_GPCM_ACS_DIV2 \ 117 | OR_GPCM_XACS \ 118 | OR_GPCM_SCY_15 \ 119 | OR_GPCM_TRLX_SET \ 120 | OR_GPCM_EHTR_SET \ 121 | OR_GPCM_EAD) 122 /* 0xffc06ff7 */ 123 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 124 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) 125 #else 126 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 127 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 128 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 129 BR_PS_16 | /* 16bit */ \ 130 BR_MS_GPCM | /* MSEL = GPCM */ \ 131 BR_V) /* valid */ 132 133 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 134 | OR_GPCM_XAM \ 135 | OR_GPCM_CSNT \ 136 | OR_GPCM_ACS_DIV2 \ 137 | OR_GPCM_XACS \ 138 | OR_GPCM_SCY_15 \ 139 | OR_GPCM_TRLX_SET \ 140 | OR_GPCM_EHTR_SET \ 141 | OR_GPCM_EAD) 142 /* 0xf8006ff7 */ 143 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 144 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 145 #endif 146 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 147 148 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 149 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ 150 | BR_PS_32 \ 151 | BR_MS_GPCM \ 152 | BR_V) 153 /* 0xF0001801 */ 154 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ 155 | OR_GPCM_SETA) 156 /* 0xfffc0208 */ 157 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE 158 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) 159 160 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 161 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 162 163 #undef CONFIG_SYS_FLASH_CHECKSUM 164 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 165 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 166 167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 168 169 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 170 #define CONFIG_SYS_RAMBOOT 171 #else 172 #undef CONFIG_SYS_RAMBOOT 173 #endif 174 175 #define CONFIG_SYS_INIT_RAM_LOCK 1 176 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 177 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 178 179 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 180 GENERATED_GBL_DATA_SIZE) 181 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 182 183 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 184 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ 185 186 /* 187 * Local Bus LCRR and LBCR regs 188 * LCRR: no DLL bypass, Clock divider is 4 189 * External Local Bus rate is 190 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 191 */ 192 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 193 #define CONFIG_SYS_LBC_LBCR 0x00000000 194 195 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 196 197 /* 198 * Serial Port 199 */ 200 #define CONFIG_CONS_INDEX 1 201 #define CONFIG_SYS_NS16550 202 #define CONFIG_SYS_NS16550_SERIAL 203 #define CONFIG_SYS_NS16550_REG_SIZE 1 204 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 205 206 #define CONFIG_SYS_BAUDRATE_TABLE \ 207 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 208 209 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 210 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 211 212 #define CONFIG_CMDLINE_EDITING /* add command line history */ 213 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 214 /* Use the HUSH parser */ 215 #define CONFIG_SYS_HUSH_PARSER 216 217 /* pass open firmware flat tree */ 218 #define CONFIG_OF_LIBFDT 219 #define CONFIG_OF_BOARD_SETUP 220 #define CONFIG_OF_STDOUT_VIA_ALIAS 221 222 /* I2C */ 223 #define CONFIG_SYS_I2C 224 #define CONFIG_SYS_I2C_FSL 225 #define CONFIG_SYS_FSL_I2C_SPEED 400000 226 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 227 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 228 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 229 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 230 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 231 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 232 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 233 234 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 235 236 /* TSEC */ 237 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 238 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 239 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 240 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 241 242 /* 243 * General PCI 244 * Addresses are mapped 1-1. 245 */ 246 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 247 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 248 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 249 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 250 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 251 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 252 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 253 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 254 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 255 256 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 257 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 258 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 259 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 260 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 261 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 262 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 263 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 264 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 265 266 #if defined(CONFIG_PCI) 267 268 #define PCI_64BIT 269 #define PCI_ONE_PCI1 270 #if defined(PCI_64BIT) 271 #undef PCI_ALL_PCI1 272 #undef PCI_TWO_PCI1 273 #undef PCI_ONE_PCI1 274 #endif 275 276 #ifndef VME_CADDY2 277 #endif 278 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 279 280 #undef CONFIG_EEPRO100 281 #undef CONFIG_TULIP 282 283 #if !defined(CONFIG_PCI_PNP) 284 #define PCI_ENET0_IOADDR 0xFIXME 285 #define PCI_ENET0_MEMADDR 0xFIXME 286 #define PCI_IDSEL_NUMBER 0xFIXME 287 #endif 288 289 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 290 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 291 292 #endif /* CONFIG_PCI */ 293 294 /* 295 * TSEC configuration 296 */ 297 #ifdef VME_CADDY2 298 #define CONFIG_E1000 299 #else 300 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 301 #endif 302 303 #if defined(CONFIG_TSEC_ENET) 304 305 #define CONFIG_GMII /* MII PHY management */ 306 #define CONFIG_TSEC1 307 #define CONFIG_TSEC1_NAME "TSEC0" 308 #define CONFIG_TSEC2 309 #define CONFIG_TSEC2_NAME "TSEC1" 310 #define CONFIG_PHY_M88E1111 311 #define TSEC1_PHY_ADDR 0x08 312 #define TSEC2_PHY_ADDR 0x10 313 #define TSEC1_PHYIDX 0 314 #define TSEC2_PHYIDX 0 315 #define TSEC1_FLAGS TSEC_GIGABIT 316 #define TSEC2_FLAGS TSEC_GIGABIT 317 318 /* Options are: TSEC[0-1] */ 319 #define CONFIG_ETHPRIME "TSEC0" 320 321 #endif /* CONFIG_TSEC_ENET */ 322 323 /* 324 * Environment 325 */ 326 #ifndef CONFIG_SYS_RAMBOOT 327 #define CONFIG_ENV_IS_IN_FLASH 328 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 329 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 330 #define CONFIG_ENV_SIZE 0x2000 331 332 /* Address and size of Redundant Environment Sector */ 333 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 334 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 335 336 #else 337 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 338 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 339 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 340 #define CONFIG_ENV_SIZE 0x2000 341 #endif 342 343 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 344 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 345 346 /* 347 * BOOTP options 348 */ 349 #define CONFIG_BOOTP_BOOTFILESIZE 350 #define CONFIG_BOOTP_BOOTPATH 351 #define CONFIG_BOOTP_GATEWAY 352 #define CONFIG_BOOTP_HOSTNAME 353 354 /* 355 * Command line configuration. 356 */ 357 #include <config_cmd_default.h> 358 359 #define CONFIG_CMD_I2C 360 #define CONFIG_CMD_MII 361 #define CONFIG_CMD_PING 362 #define CONFIG_CMD_DATE 363 #define CONFIG_SYS_RTC_BUS_NUM 0x01 364 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 365 #define CONFIG_RTC_RX8025 366 #define CONFIG_CMD_TSI148 367 368 #if defined(CONFIG_PCI) 369 #define CONFIG_CMD_PCI 370 #endif 371 372 #if defined(CONFIG_SYS_RAMBOOT) 373 #undef CONFIG_CMD_ENV 374 #undef CONFIG_CMD_LOADS 375 #endif 376 377 #define CONFIG_CMD_ELF 378 /* Pass Ethernet MAC to VxWorks */ 379 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 380 381 #undef CONFIG_WATCHDOG /* watchdog disabled */ 382 383 /* 384 * Miscellaneous configurable options 385 */ 386 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 387 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 388 389 #if defined(CONFIG_CMD_KGDB) 390 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 391 #else 392 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 393 #endif 394 395 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 396 #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ 397 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ 398 399 /* 400 * For booting Linux, the board info and command line data 401 * have to be in the first 256 MB of memory, since this is 402 * the maximum mapped by the Linux kernel during initialization. 403 */ 404 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 405 406 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 407 408 #define CONFIG_SYS_HRCW_LOW (\ 409 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 410 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 411 HRCWL_CSB_TO_CLKIN |\ 412 HRCWL_VCO_1X2 |\ 413 HRCWL_CORE_TO_CSB_2X1) 414 415 #if defined(PCI_64BIT) 416 #define CONFIG_SYS_HRCW_HIGH (\ 417 HRCWH_PCI_HOST |\ 418 HRCWH_64_BIT_PCI |\ 419 HRCWH_PCI1_ARBITER_ENABLE |\ 420 HRCWH_PCI2_ARBITER_DISABLE |\ 421 HRCWH_CORE_ENABLE |\ 422 HRCWH_FROM_0X00000100 |\ 423 HRCWH_BOOTSEQ_DISABLE |\ 424 HRCWH_SW_WATCHDOG_DISABLE |\ 425 HRCWH_ROM_LOC_LOCAL_16BIT |\ 426 HRCWH_TSEC1M_IN_GMII |\ 427 HRCWH_TSEC2M_IN_GMII) 428 #else 429 #define CONFIG_SYS_HRCW_HIGH (\ 430 HRCWH_PCI_HOST |\ 431 HRCWH_32_BIT_PCI |\ 432 HRCWH_PCI1_ARBITER_ENABLE |\ 433 HRCWH_PCI2_ARBITER_ENABLE |\ 434 HRCWH_CORE_ENABLE |\ 435 HRCWH_FROM_0X00000100 |\ 436 HRCWH_BOOTSEQ_DISABLE |\ 437 HRCWH_SW_WATCHDOG_DISABLE |\ 438 HRCWH_ROM_LOC_LOCAL_16BIT |\ 439 HRCWH_TSEC1M_IN_GMII |\ 440 HRCWH_TSEC2M_IN_GMII) 441 #endif 442 443 /* System IO Config */ 444 #define CONFIG_SYS_SICRH 0 445 #define CONFIG_SYS_SICRL SICRL_LDP_A 446 447 #define CONFIG_SYS_HID0_INIT 0x000000000 448 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 449 HID0_ENABLE_INSTRUCTION_CACHE) 450 451 #define CONFIG_SYS_HID2 HID2_HBE 452 453 #define CONFIG_SYS_GPIO1_PRELIM 454 #define CONFIG_SYS_GPIO1_DIR 0x00100000 455 #define CONFIG_SYS_GPIO1_DAT 0x00100000 456 457 #define CONFIG_SYS_GPIO2_PRELIM 458 #define CONFIG_SYS_GPIO2_DIR 0x78900000 459 #define CONFIG_SYS_GPIO2_DAT 0x70100000 460 461 #define CONFIG_HIGH_BATS /* High BATs supported */ 462 463 /* DDR @ 0x00000000 */ 464 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 465 BATL_MEMCOHERENCE) 466 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 467 BATU_VS | BATU_VP) 468 469 /* PCI @ 0x80000000 */ 470 #ifdef CONFIG_PCI 471 #define CONFIG_PCI_INDIRECT_BRIDGE 472 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ 473 BATL_MEMCOHERENCE) 474 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 475 BATU_VS | BATU_VP) 476 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ 477 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 478 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 479 BATU_VS | BATU_VP) 480 #else 481 #define CONFIG_SYS_IBAT1L (0) 482 #define CONFIG_SYS_IBAT1U (0) 483 #define CONFIG_SYS_IBAT2L (0) 484 #define CONFIG_SYS_IBAT2U (0) 485 #endif 486 487 #ifdef CONFIG_MPC83XX_PCI2 488 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ 489 BATL_MEMCOHERENCE) 490 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 491 BATU_VS | BATU_VP) 492 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ 493 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 494 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 495 BATU_VS | BATU_VP) 496 #else 497 #define CONFIG_SYS_IBAT3L (0) 498 #define CONFIG_SYS_IBAT3U (0) 499 #define CONFIG_SYS_IBAT4L (0) 500 #define CONFIG_SYS_IBAT4U (0) 501 #endif 502 503 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 504 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 505 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 506 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 507 BATU_VS | BATU_VP) 508 509 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) 510 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 511 512 #if (CONFIG_SYS_DDR_SIZE == 512) 513 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 514 BATL_PP_RW | BATL_MEMCOHERENCE) 515 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 516 BATU_BL_256M | BATU_VS | BATU_VP) 517 #else 518 #define CONFIG_SYS_IBAT7L (0) 519 #define CONFIG_SYS_IBAT7U (0) 520 #endif 521 522 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 523 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 524 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 525 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 526 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 527 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 528 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 529 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 530 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 531 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 532 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 533 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 534 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 535 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 536 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 537 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 538 539 #if defined(CONFIG_CMD_KGDB) 540 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 541 #endif 542 543 /* 544 * Environment Configuration 545 */ 546 #define CONFIG_ENV_OVERWRITE 547 548 #if defined(CONFIG_TSEC_ENET) 549 #define CONFIG_HAS_ETH0 550 #define CONFIG_HAS_ETH1 551 #endif 552 553 #define CONFIG_HOSTNAME VME8349 554 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 555 #define CONFIG_BOOTFILE "uImage" 556 557 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 558 559 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 560 #undef CONFIG_BOOTARGS /* boot command will set bootargs */ 561 562 #define CONFIG_BAUDRATE 9600 563 564 #define CONFIG_EXTRA_ENV_SETTINGS \ 565 "netdev=eth0\0" \ 566 "hostname=vme8349\0" \ 567 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 568 "nfsroot=${serverip}:${rootpath}\0" \ 569 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 570 "addip=setenv bootargs ${bootargs} " \ 571 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 572 ":${hostname}:${netdev}:off panic=1\0" \ 573 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 574 "flash_nfs=run nfsargs addip addtty;" \ 575 "bootm ${kernel_addr}\0" \ 576 "flash_self=run ramargs addip addtty;" \ 577 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 578 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 579 "bootm\0" \ 580 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 581 "update=protect off fff00000 fff3ffff; " \ 582 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 583 "upd=run load update\0" \ 584 "fdtaddr=780000\0" \ 585 "fdtfile=vme8349.dtb\0" \ 586 "" 587 588 #define CONFIG_NFSBOOTCOMMAND \ 589 "setenv bootargs root=/dev/nfs rw " \ 590 "nfsroot=$serverip:$rootpath " \ 591 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 592 "$netdev:off " \ 593 "console=$consoledev,$baudrate $othbootargs;" \ 594 "tftp $loadaddr $bootfile;" \ 595 "tftp $fdtaddr $fdtfile;" \ 596 "bootm $loadaddr - $fdtaddr" 597 598 #define CONFIG_RAMBOOTCOMMAND \ 599 "setenv bootargs root=/dev/ram rw " \ 600 "console=$consoledev,$baudrate $othbootargs;" \ 601 "tftp $ramdiskaddr $ramdiskfile;" \ 602 "tftp $loadaddr $bootfile;" \ 603 "tftp $fdtaddr $fdtfile;" \ 604 "bootm $loadaddr $ramdiskaddr $fdtaddr" 605 606 #define CONFIG_BOOTCOMMAND "run flash_self" 607 608 #ifndef __ASSEMBLY__ 609 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 610 unsigned char *buffer, int len); 611 #endif 612 613 #endif /* __CONFIG_H */ 614