1 /* 2 * esd vme8349 U-Boot configuration file 3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4 * 5 * (C) Copyright 2006-2010 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * reinhard.arlt@esd-electronics.de 9 * Based on the MPC8349EMDS config. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 /* 15 * vme8349 board configuration file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 /* 22 * Top level Makefile configuration choices 23 */ 24 #ifdef CONFIG_CADDY2 25 #define VME_CADDY2 26 #endif 27 28 /* 29 * High Level Configuration Options 30 */ 31 #define CONFIG_E300 1 /* E300 Family */ 32 #define CONFIG_MPC834x 1 /* MPC834x family */ 33 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 34 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 35 36 #define CONFIG_MISC_INIT_R 37 38 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 39 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 40 41 #define CONFIG_PCI_66M 42 #ifdef CONFIG_PCI_66M 43 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 44 #else 45 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 46 #endif 47 48 #ifndef CONFIG_SYS_CLK_FREQ 49 #ifdef CONFIG_PCI_66M 50 #define CONFIG_SYS_CLK_FREQ 66000000 51 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 52 #else 53 #define CONFIG_SYS_CLK_FREQ 33000000 54 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 55 #endif 56 #endif 57 58 #define CONFIG_SYS_IMMR 0xE0000000 59 60 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 61 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 62 #define CONFIG_SYS_MEMTEST_END 0x00100000 63 64 /* 65 * DDR Setup 66 */ 67 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 68 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 69 #define CONFIG_SPD_EEPROM 70 #define SPD_EEPROM_ADDRESS 0x54 71 #define CONFIG_SYS_READ_SPD vme8349_read_spd 72 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 73 74 /* 75 * 32-bit data path mode. 76 * 77 * Please note that using this mode for devices with the real density of 64-bit 78 * effectively reduces the amount of available memory due to the effect of 79 * wrapping around while translating address to row/columns, for example in the 80 * 256MB module the upper 128MB get aliased with contents of the lower 81 * 128MB); normally this define should be used for devices with real 32-bit 82 * data path. 83 */ 84 #undef CONFIG_DDR_32BIT 85 86 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 88 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 89 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 90 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 91 #define CONFIG_DDR_2T_TIMING 92 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 93 | DDRCDR_ODT \ 94 | DDRCDR_Q_DRN) 95 /* 0x80080001 */ 96 97 /* 98 * FLASH on the Local Bus 99 */ 100 #define CONFIG_SYS_FLASH_CFI 101 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 102 #ifdef VME_CADDY2 103 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 104 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 105 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 106 BR_PS_16 | /* 16bit */ \ 107 BR_MS_GPCM | /* MSEL = GPCM */ \ 108 BR_V) /* valid */ 109 110 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 111 | OR_GPCM_XAM \ 112 | OR_GPCM_CSNT \ 113 | OR_GPCM_ACS_DIV2 \ 114 | OR_GPCM_XACS \ 115 | OR_GPCM_SCY_15 \ 116 | OR_GPCM_TRLX_SET \ 117 | OR_GPCM_EHTR_SET \ 118 | OR_GPCM_EAD) 119 /* 0xffc06ff7 */ 120 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 121 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) 122 #else 123 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 124 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 125 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 126 BR_PS_16 | /* 16bit */ \ 127 BR_MS_GPCM | /* MSEL = GPCM */ \ 128 BR_V) /* valid */ 129 130 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 131 | OR_GPCM_XAM \ 132 | OR_GPCM_CSNT \ 133 | OR_GPCM_ACS_DIV2 \ 134 | OR_GPCM_XACS \ 135 | OR_GPCM_SCY_15 \ 136 | OR_GPCM_TRLX_SET \ 137 | OR_GPCM_EHTR_SET \ 138 | OR_GPCM_EAD) 139 /* 0xf8006ff7 */ 140 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 141 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 142 #endif 143 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 144 145 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 146 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ 147 | BR_PS_32 \ 148 | BR_MS_GPCM \ 149 | BR_V) 150 /* 0xF0001801 */ 151 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ 152 | OR_GPCM_SETA) 153 /* 0xfffc0208 */ 154 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE 155 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) 156 157 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 158 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 159 160 #undef CONFIG_SYS_FLASH_CHECKSUM 161 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 162 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 163 164 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 165 166 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 167 #define CONFIG_SYS_RAMBOOT 168 #else 169 #undef CONFIG_SYS_RAMBOOT 170 #endif 171 172 #define CONFIG_SYS_INIT_RAM_LOCK 1 173 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 174 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 175 176 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 177 GENERATED_GBL_DATA_SIZE) 178 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 179 180 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 181 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ 182 183 /* 184 * Local Bus LCRR and LBCR regs 185 * LCRR: no DLL bypass, Clock divider is 4 186 * External Local Bus rate is 187 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 188 */ 189 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 190 #define CONFIG_SYS_LBC_LBCR 0x00000000 191 192 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 193 194 /* 195 * Serial Port 196 */ 197 #define CONFIG_SYS_NS16550_SERIAL 198 #define CONFIG_SYS_NS16550_REG_SIZE 1 199 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 200 201 #define CONFIG_SYS_BAUDRATE_TABLE \ 202 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 203 204 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 205 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 206 207 /* I2C */ 208 #define CONFIG_SYS_I2C 209 #define CONFIG_SYS_I2C_FSL 210 #define CONFIG_SYS_FSL_I2C_SPEED 400000 211 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 212 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 213 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 214 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 215 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 216 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 217 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 218 219 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 220 221 /* TSEC */ 222 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 223 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 224 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 225 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 226 227 /* 228 * General PCI 229 * Addresses are mapped 1-1. 230 */ 231 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 232 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 233 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 234 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 235 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 236 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 237 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 238 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 239 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 240 241 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 242 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 243 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 244 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 245 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 246 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 247 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 248 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 249 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 250 251 #if defined(CONFIG_PCI) 252 253 #define PCI_64BIT 254 #define PCI_ONE_PCI1 255 #if defined(PCI_64BIT) 256 #undef PCI_ALL_PCI1 257 #undef PCI_TWO_PCI1 258 #undef PCI_ONE_PCI1 259 #endif 260 261 #ifndef VME_CADDY2 262 #endif 263 264 #undef CONFIG_EEPRO100 265 #undef CONFIG_TULIP 266 267 #if !defined(CONFIG_PCI_PNP) 268 #define PCI_ENET0_IOADDR 0xFIXME 269 #define PCI_ENET0_MEMADDR 0xFIXME 270 #define PCI_IDSEL_NUMBER 0xFIXME 271 #endif 272 273 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 274 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 275 276 #endif /* CONFIG_PCI */ 277 278 /* 279 * TSEC configuration 280 */ 281 282 #if defined(CONFIG_TSEC_ENET) 283 284 #define CONFIG_GMII /* MII PHY management */ 285 #define CONFIG_TSEC1 286 #define CONFIG_TSEC1_NAME "TSEC0" 287 #define CONFIG_TSEC2 288 #define CONFIG_TSEC2_NAME "TSEC1" 289 #define CONFIG_PHY_M88E1111 290 #define TSEC1_PHY_ADDR 0x08 291 #define TSEC2_PHY_ADDR 0x10 292 #define TSEC1_PHYIDX 0 293 #define TSEC2_PHYIDX 0 294 #define TSEC1_FLAGS TSEC_GIGABIT 295 #define TSEC2_FLAGS TSEC_GIGABIT 296 297 /* Options are: TSEC[0-1] */ 298 #define CONFIG_ETHPRIME "TSEC0" 299 300 #endif /* CONFIG_TSEC_ENET */ 301 302 /* 303 * Environment 304 */ 305 #ifndef CONFIG_SYS_RAMBOOT 306 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 307 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 308 #define CONFIG_ENV_SIZE 0x2000 309 310 /* Address and size of Redundant Environment Sector */ 311 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 312 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 313 314 #else 315 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 316 #define CONFIG_ENV_SIZE 0x2000 317 #endif 318 319 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 320 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 321 322 /* 323 * BOOTP options 324 */ 325 #define CONFIG_BOOTP_BOOTFILESIZE 326 327 /* 328 * Command line configuration. 329 */ 330 #define CONFIG_SYS_RTC_BUS_NUM 0x01 331 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 332 #define CONFIG_RTC_RX8025 333 334 /* Pass Ethernet MAC to VxWorks */ 335 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 336 337 #undef CONFIG_WATCHDOG /* watchdog disabled */ 338 339 /* 340 * Miscellaneous configurable options 341 */ 342 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 343 344 /* 345 * For booting Linux, the board info and command line data 346 * have to be in the first 256 MB of memory, since this is 347 * the maximum mapped by the Linux kernel during initialization. 348 */ 349 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 350 351 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 352 353 #define CONFIG_SYS_HRCW_LOW (\ 354 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 355 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 356 HRCWL_CSB_TO_CLKIN |\ 357 HRCWL_VCO_1X2 |\ 358 HRCWL_CORE_TO_CSB_2X1) 359 360 #if defined(PCI_64BIT) 361 #define CONFIG_SYS_HRCW_HIGH (\ 362 HRCWH_PCI_HOST |\ 363 HRCWH_64_BIT_PCI |\ 364 HRCWH_PCI1_ARBITER_ENABLE |\ 365 HRCWH_PCI2_ARBITER_DISABLE |\ 366 HRCWH_CORE_ENABLE |\ 367 HRCWH_FROM_0X00000100 |\ 368 HRCWH_BOOTSEQ_DISABLE |\ 369 HRCWH_SW_WATCHDOG_DISABLE |\ 370 HRCWH_ROM_LOC_LOCAL_16BIT |\ 371 HRCWH_TSEC1M_IN_GMII |\ 372 HRCWH_TSEC2M_IN_GMII) 373 #else 374 #define CONFIG_SYS_HRCW_HIGH (\ 375 HRCWH_PCI_HOST |\ 376 HRCWH_32_BIT_PCI |\ 377 HRCWH_PCI1_ARBITER_ENABLE |\ 378 HRCWH_PCI2_ARBITER_ENABLE |\ 379 HRCWH_CORE_ENABLE |\ 380 HRCWH_FROM_0X00000100 |\ 381 HRCWH_BOOTSEQ_DISABLE |\ 382 HRCWH_SW_WATCHDOG_DISABLE |\ 383 HRCWH_ROM_LOC_LOCAL_16BIT |\ 384 HRCWH_TSEC1M_IN_GMII |\ 385 HRCWH_TSEC2M_IN_GMII) 386 #endif 387 388 /* System IO Config */ 389 #define CONFIG_SYS_SICRH 0 390 #define CONFIG_SYS_SICRL SICRL_LDP_A 391 392 #define CONFIG_SYS_HID0_INIT 0x000000000 393 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 394 HID0_ENABLE_INSTRUCTION_CACHE) 395 396 #define CONFIG_SYS_HID2 HID2_HBE 397 398 #define CONFIG_SYS_GPIO1_PRELIM 399 #define CONFIG_SYS_GPIO1_DIR 0x00100000 400 #define CONFIG_SYS_GPIO1_DAT 0x00100000 401 402 #define CONFIG_SYS_GPIO2_PRELIM 403 #define CONFIG_SYS_GPIO2_DIR 0x78900000 404 #define CONFIG_SYS_GPIO2_DAT 0x70100000 405 406 #define CONFIG_HIGH_BATS /* High BATs supported */ 407 408 /* DDR @ 0x00000000 */ 409 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 410 BATL_MEMCOHERENCE) 411 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 412 BATU_VS | BATU_VP) 413 414 /* PCI @ 0x80000000 */ 415 #ifdef CONFIG_PCI 416 #define CONFIG_PCI_INDIRECT_BRIDGE 417 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ 418 BATL_MEMCOHERENCE) 419 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 420 BATU_VS | BATU_VP) 421 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ 422 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 423 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 424 BATU_VS | BATU_VP) 425 #else 426 #define CONFIG_SYS_IBAT1L (0) 427 #define CONFIG_SYS_IBAT1U (0) 428 #define CONFIG_SYS_IBAT2L (0) 429 #define CONFIG_SYS_IBAT2U (0) 430 #endif 431 432 #ifdef CONFIG_MPC83XX_PCI2 433 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ 434 BATL_MEMCOHERENCE) 435 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 436 BATU_VS | BATU_VP) 437 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ 438 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 439 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 440 BATU_VS | BATU_VP) 441 #else 442 #define CONFIG_SYS_IBAT3L (0) 443 #define CONFIG_SYS_IBAT3U (0) 444 #define CONFIG_SYS_IBAT4L (0) 445 #define CONFIG_SYS_IBAT4U (0) 446 #endif 447 448 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 449 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 450 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 451 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 452 BATU_VS | BATU_VP) 453 454 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) 455 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 456 457 #if (CONFIG_SYS_DDR_SIZE == 512) 458 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 459 BATL_PP_RW | BATL_MEMCOHERENCE) 460 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 461 BATU_BL_256M | BATU_VS | BATU_VP) 462 #else 463 #define CONFIG_SYS_IBAT7L (0) 464 #define CONFIG_SYS_IBAT7U (0) 465 #endif 466 467 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 468 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 469 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 470 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 471 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 472 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 473 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 474 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 475 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 476 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 477 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 478 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 479 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 480 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 481 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 482 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 483 484 #if defined(CONFIG_CMD_KGDB) 485 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 486 #endif 487 488 /* 489 * Environment Configuration 490 */ 491 #define CONFIG_ENV_OVERWRITE 492 493 #if defined(CONFIG_TSEC_ENET) 494 #define CONFIG_HAS_ETH0 495 #define CONFIG_HAS_ETH1 496 #endif 497 498 #define CONFIG_HOSTNAME "VME8349" 499 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 500 #define CONFIG_BOOTFILE "uImage" 501 502 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 503 504 #define CONFIG_EXTRA_ENV_SETTINGS \ 505 "netdev=eth0\0" \ 506 "hostname=vme8349\0" \ 507 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 508 "nfsroot=${serverip}:${rootpath}\0" \ 509 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 510 "addip=setenv bootargs ${bootargs} " \ 511 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 512 ":${hostname}:${netdev}:off panic=1\0" \ 513 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 514 "flash_nfs=run nfsargs addip addtty;" \ 515 "bootm ${kernel_addr}\0" \ 516 "flash_self=run ramargs addip addtty;" \ 517 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 518 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 519 "bootm\0" \ 520 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 521 "update=protect off fff00000 fff3ffff; " \ 522 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 523 "upd=run load update\0" \ 524 "fdtaddr=780000\0" \ 525 "fdtfile=vme8349.dtb\0" \ 526 "" 527 528 #define CONFIG_NFSBOOTCOMMAND \ 529 "setenv bootargs root=/dev/nfs rw " \ 530 "nfsroot=$serverip:$rootpath " \ 531 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 532 "$netdev:off " \ 533 "console=$consoledev,$baudrate $othbootargs;" \ 534 "tftp $loadaddr $bootfile;" \ 535 "tftp $fdtaddr $fdtfile;" \ 536 "bootm $loadaddr - $fdtaddr" 537 538 #define CONFIG_RAMBOOTCOMMAND \ 539 "setenv bootargs root=/dev/ram rw " \ 540 "console=$consoledev,$baudrate $othbootargs;" \ 541 "tftp $ramdiskaddr $ramdiskfile;" \ 542 "tftp $loadaddr $bootfile;" \ 543 "tftp $fdtaddr $fdtfile;" \ 544 "bootm $loadaddr $ramdiskaddr $fdtaddr" 545 546 #define CONFIG_BOOTCOMMAND "run flash_self" 547 548 #ifndef __ASSEMBLY__ 549 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 550 unsigned char *buffer, int len); 551 #endif 552 553 #endif /* __CONFIG_H */ 554