1 /* 2 * esd vme8349 U-Boot configuration file 3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4 * 5 * (C) Copyright 2006-2010 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * reinhard.arlt@esd-electronics.de 9 * Based on the MPC8349EMDS config. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 /* 15 * vme8349 board configuration file. 16 */ 17 18 #ifndef __CONFIG_H 19 #define __CONFIG_H 20 21 #define CONFIG_SYS_GENERIC_BOARD 22 #define CONFIG_DISPLAY_BOARDINFO 23 24 /* 25 * Top level Makefile configuration choices 26 */ 27 #ifdef CONFIG_CADDY2 28 #define VME_CADDY2 29 #endif 30 31 /* 32 * High Level Configuration Options 33 */ 34 #define CONFIG_E300 1 /* E300 Family */ 35 #define CONFIG_MPC834x 1 /* MPC834x family */ 36 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 37 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 38 39 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 40 41 #define CONFIG_MISC_INIT_R 42 43 #define CONFIG_PCI 44 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 45 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 46 47 #define CONFIG_PCI_66M 48 #ifdef CONFIG_PCI_66M 49 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 50 #else 51 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 52 #endif 53 54 #ifndef CONFIG_SYS_CLK_FREQ 55 #ifdef CONFIG_PCI_66M 56 #define CONFIG_SYS_CLK_FREQ 66000000 57 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 58 #else 59 #define CONFIG_SYS_CLK_FREQ 33000000 60 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 61 #endif 62 #endif 63 64 #define CONFIG_SYS_IMMR 0xE0000000 65 66 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 67 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 68 #define CONFIG_SYS_MEMTEST_END 0x00100000 69 70 /* 71 * DDR Setup 72 */ 73 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 74 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 75 #define CONFIG_SPD_EEPROM 76 #define SPD_EEPROM_ADDRESS 0x54 77 #define CONFIG_SYS_READ_SPD vme8349_read_spd 78 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 79 80 /* 81 * 32-bit data path mode. 82 * 83 * Please note that using this mode for devices with the real density of 64-bit 84 * effectively reduces the amount of available memory due to the effect of 85 * wrapping around while translating address to row/columns, for example in the 86 * 256MB module the upper 128MB get aliased with contents of the lower 87 * 128MB); normally this define should be used for devices with real 32-bit 88 * data path. 89 */ 90 #undef CONFIG_DDR_32BIT 91 92 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 94 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 96 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 97 #define CONFIG_DDR_2T_TIMING 98 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 99 | DDRCDR_ODT \ 100 | DDRCDR_Q_DRN) 101 /* 0x80080001 */ 102 103 /* 104 * FLASH on the Local Bus 105 */ 106 #define CONFIG_SYS_FLASH_CFI 107 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 108 #ifdef VME_CADDY2 109 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 110 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 111 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 112 BR_PS_16 | /* 16bit */ \ 113 BR_MS_GPCM | /* MSEL = GPCM */ \ 114 BR_V) /* valid */ 115 116 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 117 | OR_GPCM_XAM \ 118 | OR_GPCM_CSNT \ 119 | OR_GPCM_ACS_DIV2 \ 120 | OR_GPCM_XACS \ 121 | OR_GPCM_SCY_15 \ 122 | OR_GPCM_TRLX_SET \ 123 | OR_GPCM_EHTR_SET \ 124 | OR_GPCM_EAD) 125 /* 0xffc06ff7 */ 126 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 127 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) 128 #else 129 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 130 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 131 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 132 BR_PS_16 | /* 16bit */ \ 133 BR_MS_GPCM | /* MSEL = GPCM */ \ 134 BR_V) /* valid */ 135 136 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 137 | OR_GPCM_XAM \ 138 | OR_GPCM_CSNT \ 139 | OR_GPCM_ACS_DIV2 \ 140 | OR_GPCM_XACS \ 141 | OR_GPCM_SCY_15 \ 142 | OR_GPCM_TRLX_SET \ 143 | OR_GPCM_EHTR_SET \ 144 | OR_GPCM_EAD) 145 /* 0xf8006ff7 */ 146 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 147 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 148 #endif 149 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 150 151 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 152 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ 153 | BR_PS_32 \ 154 | BR_MS_GPCM \ 155 | BR_V) 156 /* 0xF0001801 */ 157 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ 158 | OR_GPCM_SETA) 159 /* 0xfffc0208 */ 160 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE 161 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) 162 163 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 164 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 165 166 #undef CONFIG_SYS_FLASH_CHECKSUM 167 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 168 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 169 170 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 171 172 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 173 #define CONFIG_SYS_RAMBOOT 174 #else 175 #undef CONFIG_SYS_RAMBOOT 176 #endif 177 178 #define CONFIG_SYS_INIT_RAM_LOCK 1 179 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 180 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 181 182 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 183 GENERATED_GBL_DATA_SIZE) 184 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 185 186 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 187 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ 188 189 /* 190 * Local Bus LCRR and LBCR regs 191 * LCRR: no DLL bypass, Clock divider is 4 192 * External Local Bus rate is 193 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 194 */ 195 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 196 #define CONFIG_SYS_LBC_LBCR 0x00000000 197 198 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 199 200 /* 201 * Serial Port 202 */ 203 #define CONFIG_CONS_INDEX 1 204 #define CONFIG_SYS_NS16550 205 #define CONFIG_SYS_NS16550_SERIAL 206 #define CONFIG_SYS_NS16550_REG_SIZE 1 207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 208 209 #define CONFIG_SYS_BAUDRATE_TABLE \ 210 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 211 212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 214 215 #define CONFIG_CMDLINE_EDITING /* add command line history */ 216 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 217 /* Use the HUSH parser */ 218 #define CONFIG_SYS_HUSH_PARSER 219 220 /* pass open firmware flat tree */ 221 #define CONFIG_OF_LIBFDT 222 #define CONFIG_OF_BOARD_SETUP 223 #define CONFIG_OF_STDOUT_VIA_ALIAS 224 225 /* I2C */ 226 #define CONFIG_SYS_I2C 227 #define CONFIG_SYS_I2C_FSL 228 #define CONFIG_SYS_FSL_I2C_SPEED 400000 229 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 230 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 231 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 232 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 233 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 234 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 235 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 236 237 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 238 239 /* TSEC */ 240 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 241 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 242 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 243 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 244 245 /* 246 * General PCI 247 * Addresses are mapped 1-1. 248 */ 249 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 250 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 251 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 252 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 253 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 254 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 255 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 256 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 257 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 258 259 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 260 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 261 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 262 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 263 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 264 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 265 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 266 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 267 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 268 269 #if defined(CONFIG_PCI) 270 271 #define PCI_64BIT 272 #define PCI_ONE_PCI1 273 #if defined(PCI_64BIT) 274 #undef PCI_ALL_PCI1 275 #undef PCI_TWO_PCI1 276 #undef PCI_ONE_PCI1 277 #endif 278 279 #ifndef VME_CADDY2 280 #endif 281 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 282 283 #undef CONFIG_EEPRO100 284 #undef CONFIG_TULIP 285 286 #if !defined(CONFIG_PCI_PNP) 287 #define PCI_ENET0_IOADDR 0xFIXME 288 #define PCI_ENET0_MEMADDR 0xFIXME 289 #define PCI_IDSEL_NUMBER 0xFIXME 290 #endif 291 292 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 293 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 294 295 #endif /* CONFIG_PCI */ 296 297 /* 298 * TSEC configuration 299 */ 300 #ifdef VME_CADDY2 301 #else 302 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 303 #endif 304 305 #if defined(CONFIG_TSEC_ENET) 306 307 #define CONFIG_GMII /* MII PHY management */ 308 #define CONFIG_TSEC1 309 #define CONFIG_TSEC1_NAME "TSEC0" 310 #define CONFIG_TSEC2 311 #define CONFIG_TSEC2_NAME "TSEC1" 312 #define CONFIG_PHY_M88E1111 313 #define TSEC1_PHY_ADDR 0x08 314 #define TSEC2_PHY_ADDR 0x10 315 #define TSEC1_PHYIDX 0 316 #define TSEC2_PHYIDX 0 317 #define TSEC1_FLAGS TSEC_GIGABIT 318 #define TSEC2_FLAGS TSEC_GIGABIT 319 320 /* Options are: TSEC[0-1] */ 321 #define CONFIG_ETHPRIME "TSEC0" 322 323 #endif /* CONFIG_TSEC_ENET */ 324 325 /* 326 * Environment 327 */ 328 #ifndef CONFIG_SYS_RAMBOOT 329 #define CONFIG_ENV_IS_IN_FLASH 330 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 331 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 332 #define CONFIG_ENV_SIZE 0x2000 333 334 /* Address and size of Redundant Environment Sector */ 335 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 336 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 337 338 #else 339 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 340 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 341 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 342 #define CONFIG_ENV_SIZE 0x2000 343 #endif 344 345 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 346 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 347 348 /* 349 * BOOTP options 350 */ 351 #define CONFIG_BOOTP_BOOTFILESIZE 352 #define CONFIG_BOOTP_BOOTPATH 353 #define CONFIG_BOOTP_GATEWAY 354 #define CONFIG_BOOTP_HOSTNAME 355 356 /* 357 * Command line configuration. 358 */ 359 #define CONFIG_CMD_I2C 360 #define CONFIG_CMD_MII 361 #define CONFIG_CMD_PING 362 #define CONFIG_CMD_DATE 363 #define CONFIG_SYS_RTC_BUS_NUM 0x01 364 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 365 #define CONFIG_RTC_RX8025 366 #define CONFIG_CMD_TSI148 367 368 #if defined(CONFIG_PCI) 369 #define CONFIG_CMD_PCI 370 #endif 371 372 #if defined(CONFIG_SYS_RAMBOOT) 373 #undef CONFIG_CMD_ENV 374 #endif 375 376 /* Pass Ethernet MAC to VxWorks */ 377 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 378 379 #undef CONFIG_WATCHDOG /* watchdog disabled */ 380 381 /* 382 * Miscellaneous configurable options 383 */ 384 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 385 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 386 387 #if defined(CONFIG_CMD_KGDB) 388 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 389 #else 390 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 391 #endif 392 393 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 394 #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ 395 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ 396 397 /* 398 * For booting Linux, the board info and command line data 399 * have to be in the first 256 MB of memory, since this is 400 * the maximum mapped by the Linux kernel during initialization. 401 */ 402 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 403 404 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 405 406 #define CONFIG_SYS_HRCW_LOW (\ 407 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 408 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 409 HRCWL_CSB_TO_CLKIN |\ 410 HRCWL_VCO_1X2 |\ 411 HRCWL_CORE_TO_CSB_2X1) 412 413 #if defined(PCI_64BIT) 414 #define CONFIG_SYS_HRCW_HIGH (\ 415 HRCWH_PCI_HOST |\ 416 HRCWH_64_BIT_PCI |\ 417 HRCWH_PCI1_ARBITER_ENABLE |\ 418 HRCWH_PCI2_ARBITER_DISABLE |\ 419 HRCWH_CORE_ENABLE |\ 420 HRCWH_FROM_0X00000100 |\ 421 HRCWH_BOOTSEQ_DISABLE |\ 422 HRCWH_SW_WATCHDOG_DISABLE |\ 423 HRCWH_ROM_LOC_LOCAL_16BIT |\ 424 HRCWH_TSEC1M_IN_GMII |\ 425 HRCWH_TSEC2M_IN_GMII) 426 #else 427 #define CONFIG_SYS_HRCW_HIGH (\ 428 HRCWH_PCI_HOST |\ 429 HRCWH_32_BIT_PCI |\ 430 HRCWH_PCI1_ARBITER_ENABLE |\ 431 HRCWH_PCI2_ARBITER_ENABLE |\ 432 HRCWH_CORE_ENABLE |\ 433 HRCWH_FROM_0X00000100 |\ 434 HRCWH_BOOTSEQ_DISABLE |\ 435 HRCWH_SW_WATCHDOG_DISABLE |\ 436 HRCWH_ROM_LOC_LOCAL_16BIT |\ 437 HRCWH_TSEC1M_IN_GMII |\ 438 HRCWH_TSEC2M_IN_GMII) 439 #endif 440 441 /* System IO Config */ 442 #define CONFIG_SYS_SICRH 0 443 #define CONFIG_SYS_SICRL SICRL_LDP_A 444 445 #define CONFIG_SYS_HID0_INIT 0x000000000 446 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 447 HID0_ENABLE_INSTRUCTION_CACHE) 448 449 #define CONFIG_SYS_HID2 HID2_HBE 450 451 #define CONFIG_SYS_GPIO1_PRELIM 452 #define CONFIG_SYS_GPIO1_DIR 0x00100000 453 #define CONFIG_SYS_GPIO1_DAT 0x00100000 454 455 #define CONFIG_SYS_GPIO2_PRELIM 456 #define CONFIG_SYS_GPIO2_DIR 0x78900000 457 #define CONFIG_SYS_GPIO2_DAT 0x70100000 458 459 #define CONFIG_HIGH_BATS /* High BATs supported */ 460 461 /* DDR @ 0x00000000 */ 462 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 463 BATL_MEMCOHERENCE) 464 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 465 BATU_VS | BATU_VP) 466 467 /* PCI @ 0x80000000 */ 468 #ifdef CONFIG_PCI 469 #define CONFIG_PCI_INDIRECT_BRIDGE 470 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ 471 BATL_MEMCOHERENCE) 472 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 473 BATU_VS | BATU_VP) 474 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ 475 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 476 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 477 BATU_VS | BATU_VP) 478 #else 479 #define CONFIG_SYS_IBAT1L (0) 480 #define CONFIG_SYS_IBAT1U (0) 481 #define CONFIG_SYS_IBAT2L (0) 482 #define CONFIG_SYS_IBAT2U (0) 483 #endif 484 485 #ifdef CONFIG_MPC83XX_PCI2 486 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ 487 BATL_MEMCOHERENCE) 488 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 489 BATU_VS | BATU_VP) 490 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ 491 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 492 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 493 BATU_VS | BATU_VP) 494 #else 495 #define CONFIG_SYS_IBAT3L (0) 496 #define CONFIG_SYS_IBAT3U (0) 497 #define CONFIG_SYS_IBAT4L (0) 498 #define CONFIG_SYS_IBAT4U (0) 499 #endif 500 501 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 502 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 503 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 504 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 505 BATU_VS | BATU_VP) 506 507 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) 508 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 509 510 #if (CONFIG_SYS_DDR_SIZE == 512) 511 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 512 BATL_PP_RW | BATL_MEMCOHERENCE) 513 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 514 BATU_BL_256M | BATU_VS | BATU_VP) 515 #else 516 #define CONFIG_SYS_IBAT7L (0) 517 #define CONFIG_SYS_IBAT7U (0) 518 #endif 519 520 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 521 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 522 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 523 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 524 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 525 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 526 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 527 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 528 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 529 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 530 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 531 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 532 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 533 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 534 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 535 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 536 537 #if defined(CONFIG_CMD_KGDB) 538 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 539 #endif 540 541 /* 542 * Environment Configuration 543 */ 544 #define CONFIG_ENV_OVERWRITE 545 546 #if defined(CONFIG_TSEC_ENET) 547 #define CONFIG_HAS_ETH0 548 #define CONFIG_HAS_ETH1 549 #endif 550 551 #define CONFIG_HOSTNAME VME8349 552 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 553 #define CONFIG_BOOTFILE "uImage" 554 555 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 556 557 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 558 #undef CONFIG_BOOTARGS /* boot command will set bootargs */ 559 560 #define CONFIG_BAUDRATE 9600 561 562 #define CONFIG_EXTRA_ENV_SETTINGS \ 563 "netdev=eth0\0" \ 564 "hostname=vme8349\0" \ 565 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 566 "nfsroot=${serverip}:${rootpath}\0" \ 567 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 568 "addip=setenv bootargs ${bootargs} " \ 569 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 570 ":${hostname}:${netdev}:off panic=1\0" \ 571 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 572 "flash_nfs=run nfsargs addip addtty;" \ 573 "bootm ${kernel_addr}\0" \ 574 "flash_self=run ramargs addip addtty;" \ 575 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 576 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 577 "bootm\0" \ 578 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 579 "update=protect off fff00000 fff3ffff; " \ 580 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 581 "upd=run load update\0" \ 582 "fdtaddr=780000\0" \ 583 "fdtfile=vme8349.dtb\0" \ 584 "" 585 586 #define CONFIG_NFSBOOTCOMMAND \ 587 "setenv bootargs root=/dev/nfs rw " \ 588 "nfsroot=$serverip:$rootpath " \ 589 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 590 "$netdev:off " \ 591 "console=$consoledev,$baudrate $othbootargs;" \ 592 "tftp $loadaddr $bootfile;" \ 593 "tftp $fdtaddr $fdtfile;" \ 594 "bootm $loadaddr - $fdtaddr" 595 596 #define CONFIG_RAMBOOTCOMMAND \ 597 "setenv bootargs root=/dev/ram rw " \ 598 "console=$consoledev,$baudrate $othbootargs;" \ 599 "tftp $ramdiskaddr $ramdiskfile;" \ 600 "tftp $loadaddr $bootfile;" \ 601 "tftp $fdtaddr $fdtfile;" \ 602 "bootm $loadaddr $ramdiskaddr $fdtaddr" 603 604 #define CONFIG_BOOTCOMMAND "run flash_self" 605 606 #ifndef __ASSEMBLY__ 607 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 608 unsigned char *buffer, int len); 609 #endif 610 611 #endif /* __CONFIG_H */ 612