1 /* 2 * esd vme8349 U-Boot configuration file 3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4 * 5 * (C) Copyright 2006-2010 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * reinhard.arlt@esd-electronics.de 9 * Based on the MPC8349EMDS config. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 /* 31 * vme8349 board configuration file. 32 */ 33 34 #ifndef __CONFIG_H 35 #define __CONFIG_H 36 37 /* 38 * Top level Makefile configuration choices 39 */ 40 #ifdef CONFIG_CADDY2 41 #define VME_CADDY2 42 #endif 43 44 /* 45 * High Level Configuration Options 46 */ 47 #define CONFIG_E300 1 /* E300 Family */ 48 #define CONFIG_MPC83xx 1 /* MPC83xx family */ 49 #define CONFIG_MPC834x 1 /* MPC834x family */ 50 #define CONFIG_MPC8349 1 /* MPC8349 specific */ 51 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 52 53 #define CONFIG_SYS_TEXT_BASE 0xFFF00000 54 55 #define CONFIG_MISC_INIT_R 56 57 #define CONFIG_PCI 58 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 59 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 60 61 #define CONFIG_PCI_66M 62 #ifdef CONFIG_PCI_66M 63 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 64 #else 65 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 66 #endif 67 68 #ifndef CONFIG_SYS_CLK_FREQ 69 #ifdef CONFIG_PCI_66M 70 #define CONFIG_SYS_CLK_FREQ 66000000 71 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 72 #else 73 #define CONFIG_SYS_CLK_FREQ 33000000 74 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 75 #endif 76 #endif 77 78 #define CONFIG_SYS_IMMR 0xE0000000 79 80 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 81 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 82 #define CONFIG_SYS_MEMTEST_END 0x00100000 83 84 /* 85 * DDR Setup 86 */ 87 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 88 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 89 #define CONFIG_SPD_EEPROM 90 #define SPD_EEPROM_ADDRESS 0x54 91 #define CONFIG_SYS_READ_SPD vme8349_read_spd 92 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 93 94 /* 95 * 32-bit data path mode. 96 * 97 * Please note that using this mode for devices with the real density of 64-bit 98 * effectively reduces the amount of available memory due to the effect of 99 * wrapping around while translating address to row/columns, for example in the 100 * 256MB module the upper 128MB get aliased with contents of the lower 101 * 128MB); normally this define should be used for devices with real 32-bit 102 * data path. 103 */ 104 #undef CONFIG_DDR_32BIT 105 106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 108 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 109 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 110 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 111 #define CONFIG_DDR_2T_TIMING 112 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 113 | DDRCDR_ODT \ 114 | DDRCDR_Q_DRN) 115 /* 0x80080001 */ 116 117 /* 118 * FLASH on the Local Bus 119 */ 120 #define CONFIG_SYS_FLASH_CFI 121 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 122 #ifdef VME_CADDY2 123 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 124 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 125 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 126 BR_PS_16 | /* 16bit */ \ 127 BR_MS_GPCM | /* MSEL = GPCM */ \ 128 BR_V) /* valid */ 129 130 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 131 | OR_GPCM_XAM \ 132 | OR_GPCM_CSNT \ 133 | OR_GPCM_ACS_DIV2 \ 134 | OR_GPCM_XACS \ 135 | OR_GPCM_SCY_15 \ 136 | OR_GPCM_TRLX_SET \ 137 | OR_GPCM_EHTR_SET \ 138 | OR_GPCM_EAD) 139 /* 0xffc06ff7 */ 140 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 141 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) 142 #else 143 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 144 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 145 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 146 BR_PS_16 | /* 16bit */ \ 147 BR_MS_GPCM | /* MSEL = GPCM */ \ 148 BR_V) /* valid */ 149 150 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 151 | OR_GPCM_XAM \ 152 | OR_GPCM_CSNT \ 153 | OR_GPCM_ACS_DIV2 \ 154 | OR_GPCM_XACS \ 155 | OR_GPCM_SCY_15 \ 156 | OR_GPCM_TRLX_SET \ 157 | OR_GPCM_EHTR_SET \ 158 | OR_GPCM_EAD) 159 /* 0xf8006ff7 */ 160 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 161 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 162 #endif 163 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 164 165 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 166 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ 167 | BR_PS_32 \ 168 | BR_MS_GPCM \ 169 | BR_V) 170 /* 0xF0001801 */ 171 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ 172 | OR_GPCM_SETA) 173 /* 0xfffc0208 */ 174 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE 175 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) 176 177 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 178 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 179 180 #undef CONFIG_SYS_FLASH_CHECKSUM 181 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 182 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 183 184 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 185 186 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 187 #define CONFIG_SYS_RAMBOOT 188 #else 189 #undef CONFIG_SYS_RAMBOOT 190 #endif 191 192 #define CONFIG_SYS_INIT_RAM_LOCK 1 193 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 194 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 195 196 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 197 GENERATED_GBL_DATA_SIZE) 198 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 199 200 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 201 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ 202 203 /* 204 * Local Bus LCRR and LBCR regs 205 * LCRR: no DLL bypass, Clock divider is 4 206 * External Local Bus rate is 207 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 208 */ 209 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 210 #define CONFIG_SYS_LBC_LBCR 0x00000000 211 212 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 213 214 /* 215 * Serial Port 216 */ 217 #define CONFIG_CONS_INDEX 1 218 #define CONFIG_SYS_NS16550 219 #define CONFIG_SYS_NS16550_SERIAL 220 #define CONFIG_SYS_NS16550_REG_SIZE 1 221 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 222 223 #define CONFIG_SYS_BAUDRATE_TABLE \ 224 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 225 226 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 227 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 228 229 #define CONFIG_CMDLINE_EDITING /* add command line history */ 230 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 231 /* Use the HUSH parser */ 232 #define CONFIG_SYS_HUSH_PARSER 233 234 /* pass open firmware flat tree */ 235 #define CONFIG_OF_LIBFDT 236 #define CONFIG_OF_BOARD_SETUP 237 #define CONFIG_OF_STDOUT_VIA_ALIAS 238 239 /* I2C */ 240 #define CONFIG_I2C_MULTI_BUS 241 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 242 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 243 #define CONFIG_FSL_I2C 244 #define CONFIG_I2C_CMD_TREE 245 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 246 #define CONFIG_SYS_I2C_SLAVE 0x7F 247 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 248 #define CONFIG_SYS_I2C1_OFFSET 0x3000 249 #define CONFIG_SYS_I2C2_OFFSET 0x3100 250 #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET 251 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 252 253 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 254 255 /* TSEC */ 256 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 257 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 258 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 259 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 260 261 /* 262 * General PCI 263 * Addresses are mapped 1-1. 264 */ 265 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 266 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 267 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 268 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 269 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 270 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 271 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 272 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 273 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 274 275 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 276 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 277 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 278 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 279 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 280 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 281 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 282 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 283 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 284 285 #if defined(CONFIG_PCI) 286 287 #define PCI_64BIT 288 #define PCI_ONE_PCI1 289 #if defined(PCI_64BIT) 290 #undef PCI_ALL_PCI1 291 #undef PCI_TWO_PCI1 292 #undef PCI_ONE_PCI1 293 #endif 294 295 #ifndef VME_CADDY2 296 #endif 297 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 298 299 #undef CONFIG_EEPRO100 300 #undef CONFIG_TULIP 301 302 #if !defined(CONFIG_PCI_PNP) 303 #define PCI_ENET0_IOADDR 0xFIXME 304 #define PCI_ENET0_MEMADDR 0xFIXME 305 #define PCI_IDSEL_NUMBER 0xFIXME 306 #endif 307 308 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 309 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 310 311 #endif /* CONFIG_PCI */ 312 313 /* 314 * TSEC configuration 315 */ 316 #ifdef VME_CADDY2 317 #define CONFIG_E1000 318 #else 319 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 320 #endif 321 322 #if defined(CONFIG_TSEC_ENET) 323 324 #define CONFIG_GMII /* MII PHY management */ 325 #define CONFIG_TSEC1 326 #define CONFIG_TSEC1_NAME "TSEC0" 327 #define CONFIG_TSEC2 328 #define CONFIG_TSEC2_NAME "TSEC1" 329 #define CONFIG_PHY_M88E1111 330 #define TSEC1_PHY_ADDR 0x08 331 #define TSEC2_PHY_ADDR 0x10 332 #define TSEC1_PHYIDX 0 333 #define TSEC2_PHYIDX 0 334 #define TSEC1_FLAGS TSEC_GIGABIT 335 #define TSEC2_FLAGS TSEC_GIGABIT 336 337 /* Options are: TSEC[0-1] */ 338 #define CONFIG_ETHPRIME "TSEC0" 339 340 #endif /* CONFIG_TSEC_ENET */ 341 342 /* 343 * Environment 344 */ 345 #ifndef CONFIG_SYS_RAMBOOT 346 #define CONFIG_ENV_IS_IN_FLASH 347 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 348 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 349 #define CONFIG_ENV_SIZE 0x2000 350 351 /* Address and size of Redundant Environment Sector */ 352 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 353 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 354 355 #else 356 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 357 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 358 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 359 #define CONFIG_ENV_SIZE 0x2000 360 #endif 361 362 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 363 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 364 365 /* 366 * BOOTP options 367 */ 368 #define CONFIG_BOOTP_BOOTFILESIZE 369 #define CONFIG_BOOTP_BOOTPATH 370 #define CONFIG_BOOTP_GATEWAY 371 #define CONFIG_BOOTP_HOSTNAME 372 373 /* 374 * Command line configuration. 375 */ 376 #include <config_cmd_default.h> 377 378 #define CONFIG_CMD_I2C 379 #define CONFIG_CMD_MII 380 #define CONFIG_CMD_PING 381 #define CONFIG_CMD_DATE 382 #define CONFIG_SYS_RTC_BUS_NUM 0x01 383 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 384 #define CONFIG_RTC_RX8025 385 #define CONFIG_CMD_TSI148 386 387 #if defined(CONFIG_PCI) 388 #define CONFIG_CMD_PCI 389 #endif 390 391 #if defined(CONFIG_SYS_RAMBOOT) 392 #undef CONFIG_CMD_ENV 393 #undef CONFIG_CMD_LOADS 394 #endif 395 396 #define CONFIG_CMD_ELF 397 /* Pass Ethernet MAC to VxWorks */ 398 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 399 400 #undef CONFIG_WATCHDOG /* watchdog disabled */ 401 402 /* 403 * Miscellaneous configurable options 404 */ 405 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 406 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 407 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 408 409 #if defined(CONFIG_CMD_KGDB) 410 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 411 #else 412 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 413 #endif 414 415 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 416 #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ 417 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ 418 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 419 420 /* 421 * For booting Linux, the board info and command line data 422 * have to be in the first 256 MB of memory, since this is 423 * the maximum mapped by the Linux kernel during initialization. 424 */ 425 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 426 427 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 428 429 #define CONFIG_SYS_HRCW_LOW (\ 430 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 431 HRCWL_DDR_TO_SCB_CLK_1X1 |\ 432 HRCWL_CSB_TO_CLKIN |\ 433 HRCWL_VCO_1X2 |\ 434 HRCWL_CORE_TO_CSB_2X1) 435 436 #if defined(PCI_64BIT) 437 #define CONFIG_SYS_HRCW_HIGH (\ 438 HRCWH_PCI_HOST |\ 439 HRCWH_64_BIT_PCI |\ 440 HRCWH_PCI1_ARBITER_ENABLE |\ 441 HRCWH_PCI2_ARBITER_DISABLE |\ 442 HRCWH_CORE_ENABLE |\ 443 HRCWH_FROM_0X00000100 |\ 444 HRCWH_BOOTSEQ_DISABLE |\ 445 HRCWH_SW_WATCHDOG_DISABLE |\ 446 HRCWH_ROM_LOC_LOCAL_16BIT |\ 447 HRCWH_TSEC1M_IN_GMII |\ 448 HRCWH_TSEC2M_IN_GMII) 449 #else 450 #define CONFIG_SYS_HRCW_HIGH (\ 451 HRCWH_PCI_HOST |\ 452 HRCWH_32_BIT_PCI |\ 453 HRCWH_PCI1_ARBITER_ENABLE |\ 454 HRCWH_PCI2_ARBITER_ENABLE |\ 455 HRCWH_CORE_ENABLE |\ 456 HRCWH_FROM_0X00000100 |\ 457 HRCWH_BOOTSEQ_DISABLE |\ 458 HRCWH_SW_WATCHDOG_DISABLE |\ 459 HRCWH_ROM_LOC_LOCAL_16BIT |\ 460 HRCWH_TSEC1M_IN_GMII |\ 461 HRCWH_TSEC2M_IN_GMII) 462 #endif 463 464 /* System IO Config */ 465 #define CONFIG_SYS_SICRH 0 466 #define CONFIG_SYS_SICRL SICRL_LDP_A 467 468 #define CONFIG_SYS_HID0_INIT 0x000000000 469 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 470 HID0_ENABLE_INSTRUCTION_CACHE) 471 472 #define CONFIG_SYS_HID2 HID2_HBE 473 474 #define CONFIG_SYS_GPIO1_PRELIM 475 #define CONFIG_SYS_GPIO1_DIR 0x00100000 476 #define CONFIG_SYS_GPIO1_DAT 0x00100000 477 478 #define CONFIG_SYS_GPIO2_PRELIM 479 #define CONFIG_SYS_GPIO2_DIR 0x78900000 480 #define CONFIG_SYS_GPIO2_DAT 0x70100000 481 482 #define CONFIG_HIGH_BATS /* High BATs supported */ 483 484 /* DDR @ 0x00000000 */ 485 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 486 BATL_MEMCOHERENCE) 487 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 488 BATU_VS | BATU_VP) 489 490 /* PCI @ 0x80000000 */ 491 #ifdef CONFIG_PCI 492 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ 493 BATL_MEMCOHERENCE) 494 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 495 BATU_VS | BATU_VP) 496 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ 497 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 498 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 499 BATU_VS | BATU_VP) 500 #else 501 #define CONFIG_SYS_IBAT1L (0) 502 #define CONFIG_SYS_IBAT1U (0) 503 #define CONFIG_SYS_IBAT2L (0) 504 #define CONFIG_SYS_IBAT2U (0) 505 #endif 506 507 #ifdef CONFIG_MPC83XX_PCI2 508 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ 509 BATL_MEMCOHERENCE) 510 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 511 BATU_VS | BATU_VP) 512 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ 513 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 514 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 515 BATU_VS | BATU_VP) 516 #else 517 #define CONFIG_SYS_IBAT3L (0) 518 #define CONFIG_SYS_IBAT3U (0) 519 #define CONFIG_SYS_IBAT4L (0) 520 #define CONFIG_SYS_IBAT4U (0) 521 #endif 522 523 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 524 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 525 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 526 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 527 BATU_VS | BATU_VP) 528 529 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) 530 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 531 532 #if (CONFIG_SYS_DDR_SIZE == 512) 533 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 534 BATL_PP_RW | BATL_MEMCOHERENCE) 535 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 536 BATU_BL_256M | BATU_VS | BATU_VP) 537 #else 538 #define CONFIG_SYS_IBAT7L (0) 539 #define CONFIG_SYS_IBAT7U (0) 540 #endif 541 542 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 543 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 544 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 545 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 546 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 547 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 548 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 549 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 550 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 551 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 552 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 553 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 554 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 555 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 556 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 557 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 558 559 #if defined(CONFIG_CMD_KGDB) 560 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 561 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 562 #endif 563 564 /* 565 * Environment Configuration 566 */ 567 #define CONFIG_ENV_OVERWRITE 568 569 #if defined(CONFIG_TSEC_ENET) 570 #define CONFIG_HAS_ETH0 571 #define CONFIG_HAS_ETH1 572 #endif 573 574 #define CONFIG_HOSTNAME VME8349 575 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 576 #define CONFIG_BOOTFILE "uImage" 577 578 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 579 580 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 581 #undef CONFIG_BOOTARGS /* boot command will set bootargs */ 582 583 #define CONFIG_BAUDRATE 9600 584 585 #define CONFIG_EXTRA_ENV_SETTINGS \ 586 "netdev=eth0\0" \ 587 "hostname=vme8349\0" \ 588 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 589 "nfsroot=${serverip}:${rootpath}\0" \ 590 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 591 "addip=setenv bootargs ${bootargs} " \ 592 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 593 ":${hostname}:${netdev}:off panic=1\0" \ 594 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 595 "flash_nfs=run nfsargs addip addtty;" \ 596 "bootm ${kernel_addr}\0" \ 597 "flash_self=run ramargs addip addtty;" \ 598 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 599 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 600 "bootm\0" \ 601 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 602 "update=protect off fff00000 fff3ffff; " \ 603 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 604 "upd=run load update\0" \ 605 "fdtaddr=780000\0" \ 606 "fdtfile=vme8349.dtb\0" \ 607 "" 608 609 #define CONFIG_NFSBOOTCOMMAND \ 610 "setenv bootargs root=/dev/nfs rw " \ 611 "nfsroot=$serverip:$rootpath " \ 612 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 613 "$netdev:off " \ 614 "console=$consoledev,$baudrate $othbootargs;" \ 615 "tftp $loadaddr $bootfile;" \ 616 "tftp $fdtaddr $fdtfile;" \ 617 "bootm $loadaddr - $fdtaddr" 618 619 #define CONFIG_RAMBOOTCOMMAND \ 620 "setenv bootargs root=/dev/ram rw " \ 621 "console=$consoledev,$baudrate $othbootargs;" \ 622 "tftp $ramdiskaddr $ramdiskfile;" \ 623 "tftp $loadaddr $bootfile;" \ 624 "tftp $fdtaddr $fdtfile;" \ 625 "bootm $loadaddr $ramdiskaddr $fdtaddr" 626 627 #define CONFIG_BOOTCOMMAND "run flash_self" 628 629 #ifndef __ASSEMBLY__ 630 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 631 unsigned char *buffer, int len); 632 #endif 633 634 #endif /* __CONFIG_H */ 635