1c2e49f70SReinhard Arlt /* 2c2e49f70SReinhard Arlt * esd vme8349 U-Boot configuration file 3c2e49f70SReinhard Arlt * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4c2e49f70SReinhard Arlt * 52ae18241SWolfgang Denk * (C) Copyright 2006-2010 6c2e49f70SReinhard Arlt * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7c2e49f70SReinhard Arlt * 8c2e49f70SReinhard Arlt * reinhard.arlt@esd-electronics.de 9c2e49f70SReinhard Arlt * Based on the MPC8349EMDS config. 10c2e49f70SReinhard Arlt * 11c2e49f70SReinhard Arlt * See file CREDITS for list of people who contributed to this 12c2e49f70SReinhard Arlt * project. 13c2e49f70SReinhard Arlt * 14c2e49f70SReinhard Arlt * This program is free software; you can redistribute it and/or 15c2e49f70SReinhard Arlt * modify it under the terms of the GNU General Public License as 16c2e49f70SReinhard Arlt * published by the Free Software Foundation; either version 2 of 17c2e49f70SReinhard Arlt * the License, or (at your option) any later version. 18c2e49f70SReinhard Arlt * 19c2e49f70SReinhard Arlt * This program is distributed in the hope that it will be useful, 20c2e49f70SReinhard Arlt * but WITHOUT ANY WARRANTY; without even the implied warranty of 21c2e49f70SReinhard Arlt * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22c2e49f70SReinhard Arlt * GNU General Public License for more details. 23c2e49f70SReinhard Arlt * 24c2e49f70SReinhard Arlt * You should have received a copy of the GNU General Public License 25c2e49f70SReinhard Arlt * along with this program; if not, write to the Free Software 26c2e49f70SReinhard Arlt * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27c2e49f70SReinhard Arlt * MA 02111-1307 USA 28c2e49f70SReinhard Arlt */ 29c2e49f70SReinhard Arlt 30c2e49f70SReinhard Arlt /* 31c2e49f70SReinhard Arlt * vme8349 board configuration file. 32c2e49f70SReinhard Arlt */ 33c2e49f70SReinhard Arlt 34c2e49f70SReinhard Arlt #ifndef __CONFIG_H 35c2e49f70SReinhard Arlt #define __CONFIG_H 36c2e49f70SReinhard Arlt 37c2e49f70SReinhard Arlt /* 381dee9be6SReinhard Arlt * Top level Makefile configuration choices 391dee9be6SReinhard Arlt */ 402ae18241SWolfgang Denk #ifdef CONFIG_CADDY2 411dee9be6SReinhard Arlt #define VME_CADDY2 421dee9be6SReinhard Arlt #endif 431dee9be6SReinhard Arlt 441dee9be6SReinhard Arlt /* 45c2e49f70SReinhard Arlt * High Level Configuration Options 46c2e49f70SReinhard Arlt */ 47c2e49f70SReinhard Arlt #define CONFIG_E300 1 /* E300 Family */ 48c2e49f70SReinhard Arlt #define CONFIG_MPC83xx 1 /* MPC83xx family */ 49c2e49f70SReinhard Arlt #define CONFIG_MPC834x 1 /* MPC834x family */ 50c2e49f70SReinhard Arlt #define CONFIG_MPC8349 1 /* MPC8349 specific */ 51c2e49f70SReinhard Arlt #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 52c2e49f70SReinhard Arlt 532ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFFF00000 542ae18241SWolfgang Denk 551dee9be6SReinhard Arlt #define CONFIG_MISC_INIT_R 561dee9be6SReinhard Arlt 57c2e49f70SReinhard Arlt #define CONFIG_PCI 58c2e49f70SReinhard Arlt /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 59c2e49f70SReinhard Arlt #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 60c2e49f70SReinhard Arlt 612ae18241SWolfgang Denk #define CONFIG_PCI_66M 622ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 63c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 64c2e49f70SReinhard Arlt #else 65c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 66c2e49f70SReinhard Arlt #endif 67c2e49f70SReinhard Arlt 68c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_CLK_FREQ 692ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 70c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 66000000 71c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 72c2e49f70SReinhard Arlt #else 73c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 33000000 74c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 75c2e49f70SReinhard Arlt #endif 76c2e49f70SReinhard Arlt #endif 77c2e49f70SReinhard Arlt 78c2e49f70SReinhard Arlt #define CONFIG_SYS_IMMR 0xE0000000 79c2e49f70SReinhard Arlt 80c2e49f70SReinhard Arlt #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 81c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 82c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_END 0x00100000 83c2e49f70SReinhard Arlt 84c2e49f70SReinhard Arlt /* 85c2e49f70SReinhard Arlt * DDR Setup 86c2e49f70SReinhard Arlt */ 87c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC /* only for ECC DDR module */ 88c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 891dee9be6SReinhard Arlt #define CONFIG_SPD_EEPROM 901dee9be6SReinhard Arlt #define SPD_EEPROM_ADDRESS 0x54 911dee9be6SReinhard Arlt #define CONFIG_SYS_READ_SPD vme8349_read_spd 92c2e49f70SReinhard Arlt #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 93c2e49f70SReinhard Arlt 94c2e49f70SReinhard Arlt /* 95c2e49f70SReinhard Arlt * 32-bit data path mode. 96c2e49f70SReinhard Arlt * 97c2e49f70SReinhard Arlt * Please note that using this mode for devices with the real density of 64-bit 98c2e49f70SReinhard Arlt * effectively reduces the amount of available memory due to the effect of 99c2e49f70SReinhard Arlt * wrapping around while translating address to row/columns, for example in the 100c2e49f70SReinhard Arlt * 256MB module the upper 128MB get aliased with contents of the lower 101c2e49f70SReinhard Arlt * 128MB); normally this define should be used for devices with real 32-bit 102c2e49f70SReinhard Arlt * data path. 103c2e49f70SReinhard Arlt */ 104c2e49f70SReinhard Arlt #undef CONFIG_DDR_32BIT 105c2e49f70SReinhard Arlt 106c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 107c2e49f70SReinhard Arlt #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 108c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 1092fef4020SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 1102fef4020SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 111c2e49f70SReinhard Arlt #define CONFIG_DDR_2T_TIMING 1122fef4020SJoe Hershberger #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 1132fef4020SJoe Hershberger | DDRCDR_ODT \ 1142fef4020SJoe Hershberger | DDRCDR_Q_DRN) 1152fef4020SJoe Hershberger /* 0x80080001 */ 116c2e49f70SReinhard Arlt 117c2e49f70SReinhard Arlt /* 118c2e49f70SReinhard Arlt * FLASH on the Local Bus 119c2e49f70SReinhard Arlt */ 120c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_CFI 121c2e49f70SReinhard Arlt #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1221dee9be6SReinhard Arlt #ifdef VME_CADDY2 1231dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 1241dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 125c2e49f70SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1267d6a0982SJoe Hershberger BR_PS_16 | /* 16bit */ \ 1277d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 128c2e49f70SReinhard Arlt BR_V) /* valid */ 129c2e49f70SReinhard Arlt 1307d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 1317d6a0982SJoe Hershberger | OR_GPCM_XAM \ 1327d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 1337d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 1347d6a0982SJoe Hershberger | OR_GPCM_XACS \ 1357d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 1367d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 1377d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 1387d6a0982SJoe Hershberger | OR_GPCM_EAD) 1397d6a0982SJoe Hershberger /* 0xffc06ff7 */ 140c2e49f70SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1417d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) 1421dee9be6SReinhard Arlt #else 1431dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 1441dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 1451dee9be6SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1467d6a0982SJoe Hershberger BR_PS_16 | /* 16bit */ \ 1477d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 1481dee9be6SReinhard Arlt BR_V) /* valid */ 1491dee9be6SReinhard Arlt 1507d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 1517d6a0982SJoe Hershberger | OR_GPCM_XAM \ 1527d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 1537d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 1547d6a0982SJoe Hershberger | OR_GPCM_XACS \ 1557d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 1567d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 1577d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 1587d6a0982SJoe Hershberger | OR_GPCM_EAD) 1597d6a0982SJoe Hershberger /* 0xf8006ff7 */ 1601dee9be6SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1617d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 1621dee9be6SReinhard Arlt #endif 1631dee9be6SReinhard Arlt /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 164c2e49f70SReinhard Arlt 1657d6a0982SJoe Hershberger #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 1667d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ 1677d6a0982SJoe Hershberger | BR_PS_32 \ 1687d6a0982SJoe Hershberger | BR_MS_GPCM \ 1697d6a0982SJoe Hershberger | BR_V) 1707d6a0982SJoe Hershberger /* 0xF0001801 */ 1717d6a0982SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ 1727d6a0982SJoe Hershberger | OR_GPCM_SETA) 1737d6a0982SJoe Hershberger /* 0xfffc0208 */ 1747d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE 1757d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) 176c2e49f70SReinhard Arlt 177c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 178c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 179c2e49f70SReinhard Arlt 180c2e49f70SReinhard Arlt #undef CONFIG_SYS_FLASH_CHECKSUM 181c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 182c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 183c2e49f70SReinhard Arlt 18414d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 185c2e49f70SReinhard Arlt 186c2e49f70SReinhard Arlt #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 187c2e49f70SReinhard Arlt #define CONFIG_SYS_RAMBOOT 188c2e49f70SReinhard Arlt #else 189c2e49f70SReinhard Arlt #undef CONFIG_SYS_RAMBOOT 190c2e49f70SReinhard Arlt #endif 191c2e49f70SReinhard Arlt 192c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_LOCK 1 193c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 194553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 195c2e49f70SReinhard Arlt 196553f0982SWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 19725ddd1fbSWolfgang Denk GENERATED_GBL_DATA_SIZE) 198c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 199c2e49f70SReinhard Arlt 200c2e49f70SReinhard Arlt #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 201*c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ 202c2e49f70SReinhard Arlt 203c2e49f70SReinhard Arlt /* 204c2e49f70SReinhard Arlt * Local Bus LCRR and LBCR regs 2051dee9be6SReinhard Arlt * LCRR: no DLL bypass, Clock divider is 4 206c2e49f70SReinhard Arlt * External Local Bus rate is 207c2e49f70SReinhard Arlt * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 208c2e49f70SReinhard Arlt */ 209c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 210c2e49f70SReinhard Arlt #define CONFIG_SYS_LBC_LBCR 0x00000000 211c2e49f70SReinhard Arlt 212c2e49f70SReinhard Arlt #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 213c2e49f70SReinhard Arlt 214c2e49f70SReinhard Arlt /* 215c2e49f70SReinhard Arlt * Serial Port 216c2e49f70SReinhard Arlt */ 217c2e49f70SReinhard Arlt #define CONFIG_CONS_INDEX 1 218c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550 219c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_SERIAL 220c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_REG_SIZE 1 221c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 222c2e49f70SReinhard Arlt 223c2e49f70SReinhard Arlt #define CONFIG_SYS_BAUDRATE_TABLE \ 224c2e49f70SReinhard Arlt {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 225c2e49f70SReinhard Arlt 226c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 227c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 228c2e49f70SReinhard Arlt 229c2e49f70SReinhard Arlt #define CONFIG_CMDLINE_EDITING /* add command line history */ 230a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 231c2e49f70SReinhard Arlt /* Use the HUSH parser */ 232c2e49f70SReinhard Arlt #define CONFIG_SYS_HUSH_PARSER 233c2e49f70SReinhard Arlt 234c2e49f70SReinhard Arlt /* pass open firmware flat tree */ 235c2e49f70SReinhard Arlt #define CONFIG_OF_LIBFDT 236c2e49f70SReinhard Arlt #define CONFIG_OF_BOARD_SETUP 237c2e49f70SReinhard Arlt #define CONFIG_OF_STDOUT_VIA_ALIAS 238c2e49f70SReinhard Arlt 239c2e49f70SReinhard Arlt /* I2C */ 240c2e49f70SReinhard Arlt #define CONFIG_I2C_MULTI_BUS 241c2e49f70SReinhard Arlt #define CONFIG_HARD_I2C /* I2C with hardware support*/ 242c2e49f70SReinhard Arlt #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 243c2e49f70SReinhard Arlt #define CONFIG_FSL_I2C 244c2e49f70SReinhard Arlt #define CONFIG_I2C_CMD_TREE 245c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 246c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_SLAVE 0x7F 247c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 248c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C1_OFFSET 0x3000 249c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C2_OFFSET 0x3100 250c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET 251efaf6f1bSPaul Gortmaker /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 252c2e49f70SReinhard Arlt 253c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 254c2e49f70SReinhard Arlt 255c2e49f70SReinhard Arlt /* TSEC */ 256c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1_OFFSET 0x24000 257c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 258c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2_OFFSET 0x25000 259c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 260c2e49f70SReinhard Arlt 261c2e49f70SReinhard Arlt /* 262c2e49f70SReinhard Arlt * General PCI 263c2e49f70SReinhard Arlt * Addresses are mapped 1-1. 264c2e49f70SReinhard Arlt */ 265c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 266c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 267c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 268c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 269c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 270c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 271c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 272c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 273c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 274c2e49f70SReinhard Arlt 275c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 276c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 277c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 278c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 279c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 280c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 281c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 282c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 283c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 284c2e49f70SReinhard Arlt 285c2e49f70SReinhard Arlt #if defined(CONFIG_PCI) 286c2e49f70SReinhard Arlt 287c2e49f70SReinhard Arlt #define PCI_64BIT 288c2e49f70SReinhard Arlt #define PCI_ONE_PCI1 289c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 290c2e49f70SReinhard Arlt #undef PCI_ALL_PCI1 291c2e49f70SReinhard Arlt #undef PCI_TWO_PCI1 292c2e49f70SReinhard Arlt #undef PCI_ONE_PCI1 293c2e49f70SReinhard Arlt #endif 294c2e49f70SReinhard Arlt 2951dee9be6SReinhard Arlt #ifndef VME_CADDY2 2961dee9be6SReinhard Arlt #endif 2971dee9be6SReinhard Arlt #define CONFIG_PCI_PNP /* do pci plug-and-play */ 298c2e49f70SReinhard Arlt 299c2e49f70SReinhard Arlt #undef CONFIG_EEPRO100 300c2e49f70SReinhard Arlt #undef CONFIG_TULIP 301c2e49f70SReinhard Arlt 302c2e49f70SReinhard Arlt #if !defined(CONFIG_PCI_PNP) 303c2e49f70SReinhard Arlt #define PCI_ENET0_IOADDR 0xFIXME 304c2e49f70SReinhard Arlt #define PCI_ENET0_MEMADDR 0xFIXME 305c2e49f70SReinhard Arlt #define PCI_IDSEL_NUMBER 0xFIXME 306c2e49f70SReinhard Arlt #endif 307c2e49f70SReinhard Arlt 3081dee9be6SReinhard Arlt #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 3091dee9be6SReinhard Arlt #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 3101dee9be6SReinhard Arlt 311c2e49f70SReinhard Arlt #endif /* CONFIG_PCI */ 312c2e49f70SReinhard Arlt 313c2e49f70SReinhard Arlt /* 314c2e49f70SReinhard Arlt * TSEC configuration 315c2e49f70SReinhard Arlt */ 3161dee9be6SReinhard Arlt #ifdef VME_CADDY2 3171dee9be6SReinhard Arlt #define CONFIG_E1000 3181dee9be6SReinhard Arlt #else 319c2e49f70SReinhard Arlt #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 3201dee9be6SReinhard Arlt #endif 321c2e49f70SReinhard Arlt 322c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 323c2e49f70SReinhard Arlt 324c2e49f70SReinhard Arlt #define CONFIG_GMII /* MII PHY management */ 325c2e49f70SReinhard Arlt #define CONFIG_TSEC1 326c2e49f70SReinhard Arlt #define CONFIG_TSEC1_NAME "TSEC0" 327c2e49f70SReinhard Arlt #define CONFIG_TSEC2 328c2e49f70SReinhard Arlt #define CONFIG_TSEC2_NAME "TSEC1" 329c2e49f70SReinhard Arlt #define CONFIG_PHY_M88E1111 330c2e49f70SReinhard Arlt #define TSEC1_PHY_ADDR 0x08 331c2e49f70SReinhard Arlt #define TSEC2_PHY_ADDR 0x10 332c2e49f70SReinhard Arlt #define TSEC1_PHYIDX 0 333c2e49f70SReinhard Arlt #define TSEC2_PHYIDX 0 334c2e49f70SReinhard Arlt #define TSEC1_FLAGS TSEC_GIGABIT 335c2e49f70SReinhard Arlt #define TSEC2_FLAGS TSEC_GIGABIT 336c2e49f70SReinhard Arlt 337c2e49f70SReinhard Arlt /* Options are: TSEC[0-1] */ 338c2e49f70SReinhard Arlt #define CONFIG_ETHPRIME "TSEC0" 339c2e49f70SReinhard Arlt 340c2e49f70SReinhard Arlt #endif /* CONFIG_TSEC_ENET */ 341c2e49f70SReinhard Arlt 342c2e49f70SReinhard Arlt /* 343c2e49f70SReinhard Arlt * Environment 344c2e49f70SReinhard Arlt */ 345c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_RAMBOOT 346c2e49f70SReinhard Arlt #define CONFIG_ENV_IS_IN_FLASH 347c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 348c2e49f70SReinhard Arlt #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 349c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 350c2e49f70SReinhard Arlt 351c2e49f70SReinhard Arlt /* Address and size of Redundant Environment Sector */ 352c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 353c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 354c2e49f70SReinhard Arlt 355c2e49f70SReinhard Arlt #else 356c2e49f70SReinhard Arlt #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 357c2e49f70SReinhard Arlt #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 358c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 359c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 360c2e49f70SReinhard Arlt #endif 361c2e49f70SReinhard Arlt 362c2e49f70SReinhard Arlt #define CONFIG_LOADS_ECHO /* echo on for serial download */ 363c2e49f70SReinhard Arlt #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 364c2e49f70SReinhard Arlt 365c2e49f70SReinhard Arlt /* 366c2e49f70SReinhard Arlt * BOOTP options 367c2e49f70SReinhard Arlt */ 368c2e49f70SReinhard Arlt #define CONFIG_BOOTP_BOOTFILESIZE 369c2e49f70SReinhard Arlt #define CONFIG_BOOTP_BOOTPATH 370c2e49f70SReinhard Arlt #define CONFIG_BOOTP_GATEWAY 371c2e49f70SReinhard Arlt #define CONFIG_BOOTP_HOSTNAME 372c2e49f70SReinhard Arlt 373c2e49f70SReinhard Arlt /* 374c2e49f70SReinhard Arlt * Command line configuration. 375c2e49f70SReinhard Arlt */ 376c2e49f70SReinhard Arlt #include <config_cmd_default.h> 377c2e49f70SReinhard Arlt 378c2e49f70SReinhard Arlt #define CONFIG_CMD_I2C 379c2e49f70SReinhard Arlt #define CONFIG_CMD_MII 380c2e49f70SReinhard Arlt #define CONFIG_CMD_PING 381c2e49f70SReinhard Arlt #define CONFIG_CMD_DATE 382c2e49f70SReinhard Arlt #define CONFIG_SYS_RTC_BUS_NUM 0x01 383c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_RTC_ADDR 0x32 384c2e49f70SReinhard Arlt #define CONFIG_RTC_RX8025 385c2e49f70SReinhard Arlt #define CONFIG_CMD_TSI148 386c2e49f70SReinhard Arlt 387c2e49f70SReinhard Arlt #if defined(CONFIG_PCI) 388c2e49f70SReinhard Arlt #define CONFIG_CMD_PCI 389c2e49f70SReinhard Arlt #endif 390c2e49f70SReinhard Arlt 391c2e49f70SReinhard Arlt #if defined(CONFIG_SYS_RAMBOOT) 392c2e49f70SReinhard Arlt #undef CONFIG_CMD_ENV 393c2e49f70SReinhard Arlt #undef CONFIG_CMD_LOADS 394c2e49f70SReinhard Arlt #endif 395c2e49f70SReinhard Arlt 396c2e49f70SReinhard Arlt #define CONFIG_CMD_ELF 397c2e49f70SReinhard Arlt /* Pass Ethernet MAC to VxWorks */ 398c2e49f70SReinhard Arlt #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 399c2e49f70SReinhard Arlt 400c2e49f70SReinhard Arlt #undef CONFIG_WATCHDOG /* watchdog disabled */ 401c2e49f70SReinhard Arlt 402c2e49f70SReinhard Arlt /* 403c2e49f70SReinhard Arlt * Miscellaneous configurable options 404c2e49f70SReinhard Arlt */ 405c2e49f70SReinhard Arlt #define CONFIG_SYS_LONGHELP /* undef to save memory */ 406c2e49f70SReinhard Arlt #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 407c2e49f70SReinhard Arlt #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 408c2e49f70SReinhard Arlt 409c2e49f70SReinhard Arlt #if defined(CONFIG_CMD_KGDB) 410c2e49f70SReinhard Arlt #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 411c2e49f70SReinhard Arlt #else 412c2e49f70SReinhard Arlt #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 413c2e49f70SReinhard Arlt #endif 414c2e49f70SReinhard Arlt 415c2e49f70SReinhard Arlt #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 416c2e49f70SReinhard Arlt #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ 417c2e49f70SReinhard Arlt #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ 418c2e49f70SReinhard Arlt #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 419c2e49f70SReinhard Arlt 420c2e49f70SReinhard Arlt /* 421c2e49f70SReinhard Arlt * For booting Linux, the board info and command line data 4229f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 423c2e49f70SReinhard Arlt * the maximum mapped by the Linux kernel during initialization. 424c2e49f70SReinhard Arlt */ 4259f530d59SIra W. Snyder #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 426c2e49f70SReinhard Arlt 427c2e49f70SReinhard Arlt #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 428c2e49f70SReinhard Arlt 429c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_LOW (\ 430c2e49f70SReinhard Arlt HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 431c2e49f70SReinhard Arlt HRCWL_DDR_TO_SCB_CLK_1X1 |\ 432c2e49f70SReinhard Arlt HRCWL_CSB_TO_CLKIN |\ 433c2e49f70SReinhard Arlt HRCWL_VCO_1X2 |\ 434c2e49f70SReinhard Arlt HRCWL_CORE_TO_CSB_2X1) 435c2e49f70SReinhard Arlt 436c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 437c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 438c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 439c2e49f70SReinhard Arlt HRCWH_64_BIT_PCI |\ 440c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 441c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_DISABLE |\ 442c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 443c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 444c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 445c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 446c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 447c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 448c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 449c2e49f70SReinhard Arlt #else 450c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 451c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 452c2e49f70SReinhard Arlt HRCWH_32_BIT_PCI |\ 453c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 454c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_ENABLE |\ 455c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 456c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 457c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 458c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 459c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 460c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 461c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 462c2e49f70SReinhard Arlt #endif 463c2e49f70SReinhard Arlt 464c2e49f70SReinhard Arlt /* System IO Config */ 465c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRH 0 466c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRL SICRL_LDP_A 467c2e49f70SReinhard Arlt 468c2e49f70SReinhard Arlt #define CONFIG_SYS_HID0_INIT 0x000000000 4691a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 4701a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE) 471c2e49f70SReinhard Arlt 472c2e49f70SReinhard Arlt #define CONFIG_SYS_HID2 HID2_HBE 473c2e49f70SReinhard Arlt 474c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_PRELIM 475c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DIR 0x00100000 476c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DAT 0x00100000 477c2e49f70SReinhard Arlt 478c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_PRELIM 479c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DIR 0x78900000 480c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DAT 0x70100000 481c2e49f70SReinhard Arlt 482c2e49f70SReinhard Arlt #define CONFIG_HIGH_BATS /* High BATs supported */ 483c2e49f70SReinhard Arlt 484c2e49f70SReinhard Arlt /* DDR @ 0x00000000 */ 48572cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 486c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 487c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 488c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 489c2e49f70SReinhard Arlt 490c2e49f70SReinhard Arlt /* PCI @ 0x80000000 */ 491c2e49f70SReinhard Arlt #ifdef CONFIG_PCI 49272cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ 493c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 494c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 495c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 49672cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ 497c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 498c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 499c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 500c2e49f70SReinhard Arlt #else 501c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1L (0) 502c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (0) 503c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2L (0) 504c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (0) 505c2e49f70SReinhard Arlt #endif 506c2e49f70SReinhard Arlt 507c2e49f70SReinhard Arlt #ifdef CONFIG_MPC83XX_PCI2 50872cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ 509c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 510c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 511c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 51272cd4087SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ 513c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 514c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 515c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 516c2e49f70SReinhard Arlt #else 517c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3L (0) 518c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (0) 519c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4L (0) 520c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (0) 521c2e49f70SReinhard Arlt #endif 522c2e49f70SReinhard Arlt 523c2e49f70SReinhard Arlt /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 52472cd4087SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 525c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 526c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 527c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 528c2e49f70SReinhard Arlt 52972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) 530c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 531c2e49f70SReinhard Arlt 532c2e49f70SReinhard Arlt #if (CONFIG_SYS_DDR_SIZE == 512) 533c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 53472cd4087SJoe Hershberger BATL_PP_RW | BATL_MEMCOHERENCE) 535c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 536c2e49f70SReinhard Arlt BATU_BL_256M | BATU_VS | BATU_VP) 537c2e49f70SReinhard Arlt #else 538c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (0) 539c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (0) 540c2e49f70SReinhard Arlt #endif 541c2e49f70SReinhard Arlt 542c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 543c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 544c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 545c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 546c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 547c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 548c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 549c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 550c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 551c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 552c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 553c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 554c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 555c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 556c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 557c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 558c2e49f70SReinhard Arlt 559c2e49f70SReinhard Arlt #if defined(CONFIG_CMD_KGDB) 560c2e49f70SReinhard Arlt #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 561c2e49f70SReinhard Arlt #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 562c2e49f70SReinhard Arlt #endif 563c2e49f70SReinhard Arlt 564c2e49f70SReinhard Arlt /* 565c2e49f70SReinhard Arlt * Environment Configuration 566c2e49f70SReinhard Arlt */ 567c2e49f70SReinhard Arlt #define CONFIG_ENV_OVERWRITE 568c2e49f70SReinhard Arlt 569c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 570c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH0 571c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH1 572c2e49f70SReinhard Arlt #endif 573c2e49f70SReinhard Arlt 574c2e49f70SReinhard Arlt #define CONFIG_HOSTNAME VME8349 5758b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/tftpboot/rootfs" 576b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 577c2e49f70SReinhard Arlt 57879f516bcSKim Phillips #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 579c2e49f70SReinhard Arlt 580c2e49f70SReinhard Arlt #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 581c2e49f70SReinhard Arlt #undef CONFIG_BOOTARGS /* boot command will set bootargs */ 582c2e49f70SReinhard Arlt 5831dee9be6SReinhard Arlt #define CONFIG_BAUDRATE 9600 584c2e49f70SReinhard Arlt 585c2e49f70SReinhard Arlt #define CONFIG_EXTRA_ENV_SETTINGS \ 586c2e49f70SReinhard Arlt "netdev=eth0\0" \ 587c2e49f70SReinhard Arlt "hostname=vme8349\0" \ 588c2e49f70SReinhard Arlt "nfsargs=setenv bootargs root=/dev/nfs rw " \ 589c2e49f70SReinhard Arlt "nfsroot=${serverip}:${rootpath}\0" \ 590c2e49f70SReinhard Arlt "ramargs=setenv bootargs root=/dev/ram rw\0" \ 591c2e49f70SReinhard Arlt "addip=setenv bootargs ${bootargs} " \ 592c2e49f70SReinhard Arlt "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 593c2e49f70SReinhard Arlt ":${hostname}:${netdev}:off panic=1\0" \ 594c2e49f70SReinhard Arlt "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 595c2e49f70SReinhard Arlt "flash_nfs=run nfsargs addip addtty;" \ 596c2e49f70SReinhard Arlt "bootm ${kernel_addr}\0" \ 597c2e49f70SReinhard Arlt "flash_self=run ramargs addip addtty;" \ 598c2e49f70SReinhard Arlt "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 599c2e49f70SReinhard Arlt "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 600c2e49f70SReinhard Arlt "bootm\0" \ 601c2e49f70SReinhard Arlt "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 602c2e49f70SReinhard Arlt "update=protect off fff00000 fff3ffff; " \ 603c2e49f70SReinhard Arlt "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 604c2e49f70SReinhard Arlt "upd=run load update\0" \ 60579f516bcSKim Phillips "fdtaddr=780000\0" \ 606c2e49f70SReinhard Arlt "fdtfile=vme8349.dtb\0" \ 607c2e49f70SReinhard Arlt "" 608c2e49f70SReinhard Arlt 609c2e49f70SReinhard Arlt #define CONFIG_NFSBOOTCOMMAND \ 610c2e49f70SReinhard Arlt "setenv bootargs root=/dev/nfs rw " \ 611c2e49f70SReinhard Arlt "nfsroot=$serverip:$rootpath " \ 612c7357a2bSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 613c7357a2bSJoe Hershberger "$netdev:off " \ 614c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 615c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 616c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 617c2e49f70SReinhard Arlt "bootm $loadaddr - $fdtaddr" 618c2e49f70SReinhard Arlt 619c2e49f70SReinhard Arlt #define CONFIG_RAMBOOTCOMMAND \ 620c2e49f70SReinhard Arlt "setenv bootargs root=/dev/ram rw " \ 621c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 622c2e49f70SReinhard Arlt "tftp $ramdiskaddr $ramdiskfile;" \ 623c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 624c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 625c2e49f70SReinhard Arlt "bootm $loadaddr $ramdiskaddr $fdtaddr" 626c2e49f70SReinhard Arlt 627c2e49f70SReinhard Arlt #define CONFIG_BOOTCOMMAND "run flash_self" 628c2e49f70SReinhard Arlt 6291dee9be6SReinhard Arlt #ifndef __ASSEMBLY__ 6301dee9be6SReinhard Arlt int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 6311dee9be6SReinhard Arlt unsigned char *buffer, int len); 6321dee9be6SReinhard Arlt #endif 6331dee9be6SReinhard Arlt 634c2e49f70SReinhard Arlt #endif /* __CONFIG_H */ 635