1c2e49f70SReinhard Arlt /* 2c2e49f70SReinhard Arlt * esd vme8349 U-Boot configuration file 3c2e49f70SReinhard Arlt * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4c2e49f70SReinhard Arlt * 52ae18241SWolfgang Denk * (C) Copyright 2006-2010 6c2e49f70SReinhard Arlt * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7c2e49f70SReinhard Arlt * 8c2e49f70SReinhard Arlt * reinhard.arlt@esd-electronics.de 9c2e49f70SReinhard Arlt * Based on the MPC8349EMDS config. 10c2e49f70SReinhard Arlt * 11c2e49f70SReinhard Arlt * See file CREDITS for list of people who contributed to this 12c2e49f70SReinhard Arlt * project. 13c2e49f70SReinhard Arlt * 14c2e49f70SReinhard Arlt * This program is free software; you can redistribute it and/or 15c2e49f70SReinhard Arlt * modify it under the terms of the GNU General Public License as 16c2e49f70SReinhard Arlt * published by the Free Software Foundation; either version 2 of 17c2e49f70SReinhard Arlt * the License, or (at your option) any later version. 18c2e49f70SReinhard Arlt * 19c2e49f70SReinhard Arlt * This program is distributed in the hope that it will be useful, 20c2e49f70SReinhard Arlt * but WITHOUT ANY WARRANTY; without even the implied warranty of 21c2e49f70SReinhard Arlt * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22c2e49f70SReinhard Arlt * GNU General Public License for more details. 23c2e49f70SReinhard Arlt * 24c2e49f70SReinhard Arlt * You should have received a copy of the GNU General Public License 25c2e49f70SReinhard Arlt * along with this program; if not, write to the Free Software 26c2e49f70SReinhard Arlt * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27c2e49f70SReinhard Arlt * MA 02111-1307 USA 28c2e49f70SReinhard Arlt */ 29c2e49f70SReinhard Arlt 30c2e49f70SReinhard Arlt /* 31c2e49f70SReinhard Arlt * vme8349 board configuration file. 32c2e49f70SReinhard Arlt */ 33c2e49f70SReinhard Arlt 34c2e49f70SReinhard Arlt #ifndef __CONFIG_H 35c2e49f70SReinhard Arlt #define __CONFIG_H 36c2e49f70SReinhard Arlt 37c2e49f70SReinhard Arlt /* 381dee9be6SReinhard Arlt * Top level Makefile configuration choices 391dee9be6SReinhard Arlt */ 402ae18241SWolfgang Denk #ifdef CONFIG_CADDY2 411dee9be6SReinhard Arlt #define VME_CADDY2 421dee9be6SReinhard Arlt #endif 431dee9be6SReinhard Arlt 441dee9be6SReinhard Arlt /* 45c2e49f70SReinhard Arlt * High Level Configuration Options 46c2e49f70SReinhard Arlt */ 47c2e49f70SReinhard Arlt #define CONFIG_E300 1 /* E300 Family */ 48c2e49f70SReinhard Arlt #define CONFIG_MPC83xx 1 /* MPC83xx family */ 49c2e49f70SReinhard Arlt #define CONFIG_MPC834x 1 /* MPC834x family */ 50c2e49f70SReinhard Arlt #define CONFIG_MPC8349 1 /* MPC8349 specific */ 51c2e49f70SReinhard Arlt #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 52c2e49f70SReinhard Arlt 532ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFFF00000 542ae18241SWolfgang Denk 551dee9be6SReinhard Arlt #define CONFIG_MISC_INIT_R 561dee9be6SReinhard Arlt 57c2e49f70SReinhard Arlt #define CONFIG_PCI 58c2e49f70SReinhard Arlt /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 59c2e49f70SReinhard Arlt #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 60c2e49f70SReinhard Arlt 612ae18241SWolfgang Denk #define CONFIG_PCI_66M 622ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 63c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 64c2e49f70SReinhard Arlt #else 65c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 66c2e49f70SReinhard Arlt #endif 67c2e49f70SReinhard Arlt 68c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_CLK_FREQ 692ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 70c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 66000000 71c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 72c2e49f70SReinhard Arlt #else 73c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 33000000 74c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 75c2e49f70SReinhard Arlt #endif 76c2e49f70SReinhard Arlt #endif 77c2e49f70SReinhard Arlt 78c2e49f70SReinhard Arlt #define CONFIG_SYS_IMMR 0xE0000000 79c2e49f70SReinhard Arlt 80c2e49f70SReinhard Arlt #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 81c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 82c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_END 0x00100000 83c2e49f70SReinhard Arlt 84c2e49f70SReinhard Arlt /* 85c2e49f70SReinhard Arlt * DDR Setup 86c2e49f70SReinhard Arlt */ 87c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC /* only for ECC DDR module */ 88c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 891dee9be6SReinhard Arlt #define CONFIG_SPD_EEPROM 901dee9be6SReinhard Arlt #define SPD_EEPROM_ADDRESS 0x54 911dee9be6SReinhard Arlt #define CONFIG_SYS_READ_SPD vme8349_read_spd 92c2e49f70SReinhard Arlt #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 93c2e49f70SReinhard Arlt 94c2e49f70SReinhard Arlt /* 95c2e49f70SReinhard Arlt * 32-bit data path mode. 96c2e49f70SReinhard Arlt * 97c2e49f70SReinhard Arlt * Please note that using this mode for devices with the real density of 64-bit 98c2e49f70SReinhard Arlt * effectively reduces the amount of available memory due to the effect of 99c2e49f70SReinhard Arlt * wrapping around while translating address to row/columns, for example in the 100c2e49f70SReinhard Arlt * 256MB module the upper 128MB get aliased with contents of the lower 101c2e49f70SReinhard Arlt * 128MB); normally this define should be used for devices with real 32-bit 102c2e49f70SReinhard Arlt * data path. 103c2e49f70SReinhard Arlt */ 104c2e49f70SReinhard Arlt #undef CONFIG_DDR_32BIT 105c2e49f70SReinhard Arlt 106c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 107c2e49f70SReinhard Arlt #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 108c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 109c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 110c2e49f70SReinhard Arlt DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 111c2e49f70SReinhard Arlt #define CONFIG_DDR_2T_TIMING 1121dee9be6SReinhard Arlt #define CONFIG_SYS_DDRCDR 0x80080001 113c2e49f70SReinhard Arlt 114c2e49f70SReinhard Arlt /* 115c2e49f70SReinhard Arlt * FLASH on the Local Bus 116c2e49f70SReinhard Arlt */ 117c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_CFI 118c2e49f70SReinhard Arlt #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1191dee9be6SReinhard Arlt #ifdef VME_CADDY2 1201dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 1211dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 122c2e49f70SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1234e7e12dfSKim Phillips (2 << BR_PS_SHIFT) | /* 16bit */ \ 124c2e49f70SReinhard Arlt BR_V) /* valid */ 125c2e49f70SReinhard Arlt 1261dee9be6SReinhard Arlt #define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */ 127c2e49f70SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1281dee9be6SReinhard Arlt #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */ 1291dee9be6SReinhard Arlt #else 1301dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 1311dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 1321dee9be6SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1334e7e12dfSKim Phillips (2 << BR_PS_SHIFT) | /* 16bit */ \ 1341dee9be6SReinhard Arlt BR_V) /* valid */ 1351dee9be6SReinhard Arlt 1361dee9be6SReinhard Arlt #define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */ 1371dee9be6SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1381dee9be6SReinhard Arlt #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */ 1391dee9be6SReinhard Arlt #endif 1401dee9be6SReinhard Arlt /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 141c2e49f70SReinhard Arlt 142c2e49f70SReinhard Arlt #define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801) 1431dee9be6SReinhard Arlt #define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200) 144c2e49f70SReinhard Arlt #define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000 1451dee9be6SReinhard Arlt #define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011) 146c2e49f70SReinhard Arlt 147c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 148c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 149c2e49f70SReinhard Arlt 150c2e49f70SReinhard Arlt #undef CONFIG_SYS_FLASH_CHECKSUM 151c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 152c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 153c2e49f70SReinhard Arlt 15414d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 155c2e49f70SReinhard Arlt 156c2e49f70SReinhard Arlt #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 157c2e49f70SReinhard Arlt #define CONFIG_SYS_RAMBOOT 158c2e49f70SReinhard Arlt #else 159c2e49f70SReinhard Arlt #undef CONFIG_SYS_RAMBOOT 160c2e49f70SReinhard Arlt #endif 161c2e49f70SReinhard Arlt 162c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_LOCK 1 163c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 164553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 165c2e49f70SReinhard Arlt 166553f0982SWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 16725ddd1fbSWolfgang Denk GENERATED_GBL_DATA_SIZE) 168c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 169c2e49f70SReinhard Arlt 170c2e49f70SReinhard Arlt #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 171c2e49f70SReinhard Arlt #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Malloc size */ 172c2e49f70SReinhard Arlt 173c2e49f70SReinhard Arlt /* 174c2e49f70SReinhard Arlt * Local Bus LCRR and LBCR regs 1751dee9be6SReinhard Arlt * LCRR: no DLL bypass, Clock divider is 4 176c2e49f70SReinhard Arlt * External Local Bus rate is 177c2e49f70SReinhard Arlt * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 178c2e49f70SReinhard Arlt */ 179c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 180c2e49f70SReinhard Arlt #define CONFIG_SYS_LBC_LBCR 0x00000000 181c2e49f70SReinhard Arlt 182c2e49f70SReinhard Arlt #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 183c2e49f70SReinhard Arlt 184c2e49f70SReinhard Arlt /* 185c2e49f70SReinhard Arlt * Serial Port 186c2e49f70SReinhard Arlt */ 187c2e49f70SReinhard Arlt #define CONFIG_CONS_INDEX 1 188c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550 189c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_SERIAL 190c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_REG_SIZE 1 191c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 192c2e49f70SReinhard Arlt 193c2e49f70SReinhard Arlt #define CONFIG_SYS_BAUDRATE_TABLE \ 194c2e49f70SReinhard Arlt {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 195c2e49f70SReinhard Arlt 196c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 197c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 198c2e49f70SReinhard Arlt 199c2e49f70SReinhard Arlt #define CONFIG_CMDLINE_EDITING /* add command line history */ 200a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 201c2e49f70SReinhard Arlt /* Use the HUSH parser */ 202c2e49f70SReinhard Arlt #define CONFIG_SYS_HUSH_PARSER 203c2e49f70SReinhard Arlt #ifdef CONFIG_SYS_HUSH_PARSER 204c2e49f70SReinhard Arlt #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 205c2e49f70SReinhard Arlt #endif 206c2e49f70SReinhard Arlt 207c2e49f70SReinhard Arlt /* pass open firmware flat tree */ 208c2e49f70SReinhard Arlt #define CONFIG_OF_LIBFDT 209c2e49f70SReinhard Arlt #define CONFIG_OF_BOARD_SETUP 210c2e49f70SReinhard Arlt #define CONFIG_OF_STDOUT_VIA_ALIAS 211c2e49f70SReinhard Arlt 212c2e49f70SReinhard Arlt /* I2C */ 213c2e49f70SReinhard Arlt #define CONFIG_I2C_MULTI_BUS 214c2e49f70SReinhard Arlt #define CONFIG_HARD_I2C /* I2C with hardware support*/ 215c2e49f70SReinhard Arlt #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 216c2e49f70SReinhard Arlt #define CONFIG_FSL_I2C 217c2e49f70SReinhard Arlt #define CONFIG_I2C_CMD_TREE 218c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 219c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_SLAVE 0x7F 220c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 221c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C1_OFFSET 0x3000 222c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C2_OFFSET 0x3100 223c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET 224efaf6f1bSPaul Gortmaker /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 225c2e49f70SReinhard Arlt 226c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 227c2e49f70SReinhard Arlt 228c2e49f70SReinhard Arlt /* TSEC */ 229c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1_OFFSET 0x24000 230c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 231c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2_OFFSET 0x25000 232c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 233c2e49f70SReinhard Arlt 234c2e49f70SReinhard Arlt /* 235c2e49f70SReinhard Arlt * General PCI 236c2e49f70SReinhard Arlt * Addresses are mapped 1-1. 237c2e49f70SReinhard Arlt */ 238c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 239c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 240c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 241c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 242c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 243c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 244c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 245c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 246c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 247c2e49f70SReinhard Arlt 248c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 249c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 250c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 251c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 252c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 253c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 254c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 255c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 256c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 257c2e49f70SReinhard Arlt 258c2e49f70SReinhard Arlt #if defined(CONFIG_PCI) 259c2e49f70SReinhard Arlt 260c2e49f70SReinhard Arlt #define PCI_64BIT 261c2e49f70SReinhard Arlt #define PCI_ONE_PCI1 262c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 263c2e49f70SReinhard Arlt #undef PCI_ALL_PCI1 264c2e49f70SReinhard Arlt #undef PCI_TWO_PCI1 265c2e49f70SReinhard Arlt #undef PCI_ONE_PCI1 266c2e49f70SReinhard Arlt #endif 267c2e49f70SReinhard Arlt 2681dee9be6SReinhard Arlt #ifndef VME_CADDY2 2691dee9be6SReinhard Arlt #endif 2701dee9be6SReinhard Arlt #define CONFIG_PCI_PNP /* do pci plug-and-play */ 271c2e49f70SReinhard Arlt 272c2e49f70SReinhard Arlt #undef CONFIG_EEPRO100 273c2e49f70SReinhard Arlt #undef CONFIG_TULIP 274c2e49f70SReinhard Arlt 275c2e49f70SReinhard Arlt #if !defined(CONFIG_PCI_PNP) 276c2e49f70SReinhard Arlt #define PCI_ENET0_IOADDR 0xFIXME 277c2e49f70SReinhard Arlt #define PCI_ENET0_MEMADDR 0xFIXME 278c2e49f70SReinhard Arlt #define PCI_IDSEL_NUMBER 0xFIXME 279c2e49f70SReinhard Arlt #endif 280c2e49f70SReinhard Arlt 2811dee9be6SReinhard Arlt #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 2821dee9be6SReinhard Arlt #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 2831dee9be6SReinhard Arlt 284c2e49f70SReinhard Arlt #endif /* CONFIG_PCI */ 285c2e49f70SReinhard Arlt 286c2e49f70SReinhard Arlt /* 287c2e49f70SReinhard Arlt * TSEC configuration 288c2e49f70SReinhard Arlt */ 2891dee9be6SReinhard Arlt #ifdef VME_CADDY2 2901dee9be6SReinhard Arlt #define CONFIG_E1000 2911dee9be6SReinhard Arlt #else 292c2e49f70SReinhard Arlt #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 2931dee9be6SReinhard Arlt #endif 294c2e49f70SReinhard Arlt 295c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 296c2e49f70SReinhard Arlt 297c2e49f70SReinhard Arlt #define CONFIG_GMII /* MII PHY management */ 298c2e49f70SReinhard Arlt #define CONFIG_TSEC1 299c2e49f70SReinhard Arlt #define CONFIG_TSEC1_NAME "TSEC0" 300c2e49f70SReinhard Arlt #define CONFIG_TSEC2 301c2e49f70SReinhard Arlt #define CONFIG_TSEC2_NAME "TSEC1" 302c2e49f70SReinhard Arlt #define CONFIG_PHY_M88E1111 303c2e49f70SReinhard Arlt #define TSEC1_PHY_ADDR 0x08 304c2e49f70SReinhard Arlt #define TSEC2_PHY_ADDR 0x10 305c2e49f70SReinhard Arlt #define TSEC1_PHYIDX 0 306c2e49f70SReinhard Arlt #define TSEC2_PHYIDX 0 307c2e49f70SReinhard Arlt #define TSEC1_FLAGS TSEC_GIGABIT 308c2e49f70SReinhard Arlt #define TSEC2_FLAGS TSEC_GIGABIT 309c2e49f70SReinhard Arlt 310c2e49f70SReinhard Arlt /* Options are: TSEC[0-1] */ 311c2e49f70SReinhard Arlt #define CONFIG_ETHPRIME "TSEC0" 312c2e49f70SReinhard Arlt 313c2e49f70SReinhard Arlt #endif /* CONFIG_TSEC_ENET */ 314c2e49f70SReinhard Arlt 315c2e49f70SReinhard Arlt /* 316c2e49f70SReinhard Arlt * Environment 317c2e49f70SReinhard Arlt */ 318c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_RAMBOOT 319c2e49f70SReinhard Arlt #define CONFIG_ENV_IS_IN_FLASH 320c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 321c2e49f70SReinhard Arlt #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 322c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 323c2e49f70SReinhard Arlt 324c2e49f70SReinhard Arlt /* Address and size of Redundant Environment Sector */ 325c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 326c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 327c2e49f70SReinhard Arlt 328c2e49f70SReinhard Arlt #else 329c2e49f70SReinhard Arlt #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 330c2e49f70SReinhard Arlt #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 331c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 332c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 333c2e49f70SReinhard Arlt #endif 334c2e49f70SReinhard Arlt 335c2e49f70SReinhard Arlt #define CONFIG_LOADS_ECHO /* echo on for serial download */ 336c2e49f70SReinhard Arlt #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 337c2e49f70SReinhard Arlt 338c2e49f70SReinhard Arlt /* 339c2e49f70SReinhard Arlt * BOOTP options 340c2e49f70SReinhard Arlt */ 341c2e49f70SReinhard Arlt #define CONFIG_BOOTP_BOOTFILESIZE 342c2e49f70SReinhard Arlt #define CONFIG_BOOTP_BOOTPATH 343c2e49f70SReinhard Arlt #define CONFIG_BOOTP_GATEWAY 344c2e49f70SReinhard Arlt #define CONFIG_BOOTP_HOSTNAME 345c2e49f70SReinhard Arlt 346c2e49f70SReinhard Arlt /* 347c2e49f70SReinhard Arlt * Command line configuration. 348c2e49f70SReinhard Arlt */ 349c2e49f70SReinhard Arlt #include <config_cmd_default.h> 350c2e49f70SReinhard Arlt 351c2e49f70SReinhard Arlt #define CONFIG_CMD_I2C 352c2e49f70SReinhard Arlt #define CONFIG_CMD_MII 353c2e49f70SReinhard Arlt #define CONFIG_CMD_PING 354c2e49f70SReinhard Arlt #define CONFIG_CMD_DATE 355c2e49f70SReinhard Arlt #define CONFIG_SYS_RTC_BUS_NUM 0x01 356c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_RTC_ADDR 0x32 357c2e49f70SReinhard Arlt #define CONFIG_RTC_RX8025 358c2e49f70SReinhard Arlt #define CONFIG_CMD_TSI148 359c2e49f70SReinhard Arlt 360c2e49f70SReinhard Arlt #if defined(CONFIG_PCI) 361c2e49f70SReinhard Arlt #define CONFIG_CMD_PCI 362c2e49f70SReinhard Arlt #endif 363c2e49f70SReinhard Arlt 364c2e49f70SReinhard Arlt #if defined(CONFIG_SYS_RAMBOOT) 365c2e49f70SReinhard Arlt #undef CONFIG_CMD_ENV 366c2e49f70SReinhard Arlt #undef CONFIG_CMD_LOADS 367c2e49f70SReinhard Arlt #endif 368c2e49f70SReinhard Arlt 369c2e49f70SReinhard Arlt #define CONFIG_CMD_ELF 370c2e49f70SReinhard Arlt /* Pass Ethernet MAC to VxWorks */ 371c2e49f70SReinhard Arlt #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 372c2e49f70SReinhard Arlt 373c2e49f70SReinhard Arlt #undef CONFIG_WATCHDOG /* watchdog disabled */ 374c2e49f70SReinhard Arlt 375c2e49f70SReinhard Arlt /* 376c2e49f70SReinhard Arlt * Miscellaneous configurable options 377c2e49f70SReinhard Arlt */ 378c2e49f70SReinhard Arlt #define CONFIG_SYS_LONGHELP /* undef to save memory */ 379c2e49f70SReinhard Arlt #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 380c2e49f70SReinhard Arlt #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 381c2e49f70SReinhard Arlt 382c2e49f70SReinhard Arlt #if defined(CONFIG_CMD_KGDB) 383c2e49f70SReinhard Arlt #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 384c2e49f70SReinhard Arlt #else 385c2e49f70SReinhard Arlt #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 386c2e49f70SReinhard Arlt #endif 387c2e49f70SReinhard Arlt 388c2e49f70SReinhard Arlt #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 389c2e49f70SReinhard Arlt #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ 390c2e49f70SReinhard Arlt #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ 391c2e49f70SReinhard Arlt #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 392c2e49f70SReinhard Arlt 393c2e49f70SReinhard Arlt /* 394c2e49f70SReinhard Arlt * For booting Linux, the board info and command line data 3959f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 396c2e49f70SReinhard Arlt * the maximum mapped by the Linux kernel during initialization. 397c2e49f70SReinhard Arlt */ 3989f530d59SIra W. Snyder #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 399c2e49f70SReinhard Arlt 400c2e49f70SReinhard Arlt #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 401c2e49f70SReinhard Arlt 402c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_LOW (\ 403c2e49f70SReinhard Arlt HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 404c2e49f70SReinhard Arlt HRCWL_DDR_TO_SCB_CLK_1X1 |\ 405c2e49f70SReinhard Arlt HRCWL_CSB_TO_CLKIN |\ 406c2e49f70SReinhard Arlt HRCWL_VCO_1X2 |\ 407c2e49f70SReinhard Arlt HRCWL_CORE_TO_CSB_2X1) 408c2e49f70SReinhard Arlt 409c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 410c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 411c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 412c2e49f70SReinhard Arlt HRCWH_64_BIT_PCI |\ 413c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 414c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_DISABLE |\ 415c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 416c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 417c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 418c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 419c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 420c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 421c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 422c2e49f70SReinhard Arlt #else 423c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 424c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 425c2e49f70SReinhard Arlt HRCWH_32_BIT_PCI |\ 426c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 427c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_ENABLE |\ 428c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 429c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 430c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 431c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 432c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 433c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 434c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 435c2e49f70SReinhard Arlt #endif 436c2e49f70SReinhard Arlt 437c2e49f70SReinhard Arlt /* System IO Config */ 438c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRH 0 439c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRL SICRL_LDP_A 440c2e49f70SReinhard Arlt 441c2e49f70SReinhard Arlt #define CONFIG_SYS_HID0_INIT 0x000000000 4421a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 4431a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE) 444c2e49f70SReinhard Arlt 445c2e49f70SReinhard Arlt #define CONFIG_SYS_HID2 HID2_HBE 446c2e49f70SReinhard Arlt 447c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_PRELIM 448c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DIR 0x00100000 449c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DAT 0x00100000 450c2e49f70SReinhard Arlt 451c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_PRELIM 452c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DIR 0x78900000 453c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DAT 0x70100000 454c2e49f70SReinhard Arlt 455c2e49f70SReinhard Arlt #define CONFIG_HIGH_BATS /* High BATs supported */ 456c2e49f70SReinhard Arlt 457c2e49f70SReinhard Arlt /* DDR @ 0x00000000 */ 458c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ 459c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 460c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 461c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 462c2e49f70SReinhard Arlt 463c2e49f70SReinhard Arlt /* PCI @ 0x80000000 */ 464c2e49f70SReinhard Arlt #ifdef CONFIG_PCI 465c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \ 466c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 467c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 468c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 469c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \ 470c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 471c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 472c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 473c2e49f70SReinhard Arlt #else 474c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1L (0) 475c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (0) 476c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2L (0) 477c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (0) 478c2e49f70SReinhard Arlt #endif 479c2e49f70SReinhard Arlt 480c2e49f70SReinhard Arlt #ifdef CONFIG_MPC83XX_PCI2 481c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \ 482c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 483c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 484c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 485c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \ 486c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 487c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 488c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 489c2e49f70SReinhard Arlt #else 490c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3L (0) 491c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (0) 492c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4L (0) 493c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (0) 494c2e49f70SReinhard Arlt #endif 495c2e49f70SReinhard Arlt 496c2e49f70SReinhard Arlt /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 497c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 498c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 499c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 500c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 501c2e49f70SReinhard Arlt 502c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 503c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 504c2e49f70SReinhard Arlt 505c2e49f70SReinhard Arlt #if (CONFIG_SYS_DDR_SIZE == 512) 506c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 507c2e49f70SReinhard Arlt BATL_PP_10 | BATL_MEMCOHERENCE) 508c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 509c2e49f70SReinhard Arlt BATU_BL_256M | BATU_VS | BATU_VP) 510c2e49f70SReinhard Arlt #else 511c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (0) 512c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (0) 513c2e49f70SReinhard Arlt #endif 514c2e49f70SReinhard Arlt 515c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 516c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 517c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 518c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 519c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 520c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 521c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 522c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 523c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 524c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 525c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 526c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 527c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 528c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 529c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 530c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 531c2e49f70SReinhard Arlt 532c2e49f70SReinhard Arlt #if defined(CONFIG_CMD_KGDB) 533c2e49f70SReinhard Arlt #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 534c2e49f70SReinhard Arlt #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 535c2e49f70SReinhard Arlt #endif 536c2e49f70SReinhard Arlt 537c2e49f70SReinhard Arlt /* 538c2e49f70SReinhard Arlt * Environment Configuration 539c2e49f70SReinhard Arlt */ 540c2e49f70SReinhard Arlt #define CONFIG_ENV_OVERWRITE 541c2e49f70SReinhard Arlt 542c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 543c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH0 544c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH1 545c2e49f70SReinhard Arlt #endif 546c2e49f70SReinhard Arlt 547c2e49f70SReinhard Arlt #define CONFIG_HOSTNAME VME8349 5488b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/tftpboot/rootfs" 549b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 550c2e49f70SReinhard Arlt 55179f516bcSKim Phillips #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 552c2e49f70SReinhard Arlt 553c2e49f70SReinhard Arlt #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 554c2e49f70SReinhard Arlt #undef CONFIG_BOOTARGS /* boot command will set bootargs */ 555c2e49f70SReinhard Arlt 5561dee9be6SReinhard Arlt #define CONFIG_BAUDRATE 9600 557c2e49f70SReinhard Arlt 558c2e49f70SReinhard Arlt #define CONFIG_EXTRA_ENV_SETTINGS \ 559c2e49f70SReinhard Arlt "netdev=eth0\0" \ 560c2e49f70SReinhard Arlt "hostname=vme8349\0" \ 561c2e49f70SReinhard Arlt "nfsargs=setenv bootargs root=/dev/nfs rw " \ 562c2e49f70SReinhard Arlt "nfsroot=${serverip}:${rootpath}\0" \ 563c2e49f70SReinhard Arlt "ramargs=setenv bootargs root=/dev/ram rw\0" \ 564c2e49f70SReinhard Arlt "addip=setenv bootargs ${bootargs} " \ 565c2e49f70SReinhard Arlt "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 566c2e49f70SReinhard Arlt ":${hostname}:${netdev}:off panic=1\0" \ 567c2e49f70SReinhard Arlt "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 568c2e49f70SReinhard Arlt "flash_nfs=run nfsargs addip addtty;" \ 569c2e49f70SReinhard Arlt "bootm ${kernel_addr}\0" \ 570c2e49f70SReinhard Arlt "flash_self=run ramargs addip addtty;" \ 571c2e49f70SReinhard Arlt "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 572c2e49f70SReinhard Arlt "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 573c2e49f70SReinhard Arlt "bootm\0" \ 574c2e49f70SReinhard Arlt "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 575c2e49f70SReinhard Arlt "update=protect off fff00000 fff3ffff; " \ 576c2e49f70SReinhard Arlt "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 577c2e49f70SReinhard Arlt "upd=run load update\0" \ 57879f516bcSKim Phillips "fdtaddr=780000\0" \ 579c2e49f70SReinhard Arlt "fdtfile=vme8349.dtb\0" \ 580c2e49f70SReinhard Arlt "" 581c2e49f70SReinhard Arlt 582c2e49f70SReinhard Arlt #define CONFIG_NFSBOOTCOMMAND \ 583c2e49f70SReinhard Arlt "setenv bootargs root=/dev/nfs rw " \ 584c2e49f70SReinhard Arlt "nfsroot=$serverip:$rootpath " \ 585*c7357a2bSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 586*c7357a2bSJoe Hershberger "$netdev:off " \ 587c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 588c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 589c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 590c2e49f70SReinhard Arlt "bootm $loadaddr - $fdtaddr" 591c2e49f70SReinhard Arlt 592c2e49f70SReinhard Arlt #define CONFIG_RAMBOOTCOMMAND \ 593c2e49f70SReinhard Arlt "setenv bootargs root=/dev/ram rw " \ 594c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 595c2e49f70SReinhard Arlt "tftp $ramdiskaddr $ramdiskfile;" \ 596c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 597c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 598c2e49f70SReinhard Arlt "bootm $loadaddr $ramdiskaddr $fdtaddr" 599c2e49f70SReinhard Arlt 600c2e49f70SReinhard Arlt #define CONFIG_BOOTCOMMAND "run flash_self" 601c2e49f70SReinhard Arlt 6021dee9be6SReinhard Arlt #ifndef __ASSEMBLY__ 6031dee9be6SReinhard Arlt int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 6041dee9be6SReinhard Arlt unsigned char *buffer, int len); 6051dee9be6SReinhard Arlt #endif 6061dee9be6SReinhard Arlt 607c2e49f70SReinhard Arlt #endif /* __CONFIG_H */ 608