1*c2e49f70SReinhard Arlt /* 2*c2e49f70SReinhard Arlt * esd vme8349 U-Boot configuration file 3*c2e49f70SReinhard Arlt * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4*c2e49f70SReinhard Arlt * 5*c2e49f70SReinhard Arlt * (C) Copyright 2006 6*c2e49f70SReinhard Arlt * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7*c2e49f70SReinhard Arlt * 8*c2e49f70SReinhard Arlt * reinhard.arlt@esd-electronics.de 9*c2e49f70SReinhard Arlt * Based on the MPC8349EMDS config. 10*c2e49f70SReinhard Arlt * 11*c2e49f70SReinhard Arlt * See file CREDITS for list of people who contributed to this 12*c2e49f70SReinhard Arlt * project. 13*c2e49f70SReinhard Arlt * 14*c2e49f70SReinhard Arlt * This program is free software; you can redistribute it and/or 15*c2e49f70SReinhard Arlt * modify it under the terms of the GNU General Public License as 16*c2e49f70SReinhard Arlt * published by the Free Software Foundation; either version 2 of 17*c2e49f70SReinhard Arlt * the License, or (at your option) any later version. 18*c2e49f70SReinhard Arlt * 19*c2e49f70SReinhard Arlt * This program is distributed in the hope that it will be useful, 20*c2e49f70SReinhard Arlt * but WITHOUT ANY WARRANTY; without even the implied warranty of 21*c2e49f70SReinhard Arlt * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22*c2e49f70SReinhard Arlt * GNU General Public License for more details. 23*c2e49f70SReinhard Arlt * 24*c2e49f70SReinhard Arlt * You should have received a copy of the GNU General Public License 25*c2e49f70SReinhard Arlt * along with this program; if not, write to the Free Software 26*c2e49f70SReinhard Arlt * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27*c2e49f70SReinhard Arlt * MA 02111-1307 USA 28*c2e49f70SReinhard Arlt */ 29*c2e49f70SReinhard Arlt 30*c2e49f70SReinhard Arlt /* 31*c2e49f70SReinhard Arlt * vme8349 board configuration file. 32*c2e49f70SReinhard Arlt */ 33*c2e49f70SReinhard Arlt 34*c2e49f70SReinhard Arlt #ifndef __CONFIG_H 35*c2e49f70SReinhard Arlt #define __CONFIG_H 36*c2e49f70SReinhard Arlt 37*c2e49f70SReinhard Arlt /* 38*c2e49f70SReinhard Arlt * High Level Configuration Options 39*c2e49f70SReinhard Arlt */ 40*c2e49f70SReinhard Arlt #define CONFIG_E300 1 /* E300 Family */ 41*c2e49f70SReinhard Arlt #define CONFIG_MPC83xx 1 /* MPC83xx family */ 42*c2e49f70SReinhard Arlt #define CONFIG_MPC834x 1 /* MPC834x family */ 43*c2e49f70SReinhard Arlt #define CONFIG_MPC8349 1 /* MPC8349 specific */ 44*c2e49f70SReinhard Arlt #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 45*c2e49f70SReinhard Arlt 46*c2e49f70SReinhard Arlt #define CONFIG_PCI 47*c2e49f70SReinhard Arlt /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 48*c2e49f70SReinhard Arlt #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 49*c2e49f70SReinhard Arlt 50*c2e49f70SReinhard Arlt #define PCI_66M 51*c2e49f70SReinhard Arlt #ifdef PCI_66M 52*c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 53*c2e49f70SReinhard Arlt #else 54*c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 55*c2e49f70SReinhard Arlt #endif 56*c2e49f70SReinhard Arlt 57*c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_CLK_FREQ 58*c2e49f70SReinhard Arlt #ifdef PCI_66M 59*c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 66000000 60*c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 61*c2e49f70SReinhard Arlt #else 62*c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 33000000 63*c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 64*c2e49f70SReinhard Arlt #endif 65*c2e49f70SReinhard Arlt #endif 66*c2e49f70SReinhard Arlt 67*c2e49f70SReinhard Arlt #define CONFIG_SYS_IMMR 0xE0000000 68*c2e49f70SReinhard Arlt 69*c2e49f70SReinhard Arlt #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 70*c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 71*c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_END 0x00100000 72*c2e49f70SReinhard Arlt 73*c2e49f70SReinhard Arlt /* 74*c2e49f70SReinhard Arlt * DDR Setup 75*c2e49f70SReinhard Arlt */ 76*c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC /* only for ECC DDR module */ 77*c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 78*c2e49f70SReinhard Arlt #undef CONFIG_SPD_EEPROM /* dont use SPD EEPROM for DDR setup*/ 79*c2e49f70SReinhard Arlt #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 80*c2e49f70SReinhard Arlt 81*c2e49f70SReinhard Arlt /* 82*c2e49f70SReinhard Arlt * 32-bit data path mode. 83*c2e49f70SReinhard Arlt * 84*c2e49f70SReinhard Arlt * Please note that using this mode for devices with the real density of 64-bit 85*c2e49f70SReinhard Arlt * effectively reduces the amount of available memory due to the effect of 86*c2e49f70SReinhard Arlt * wrapping around while translating address to row/columns, for example in the 87*c2e49f70SReinhard Arlt * 256MB module the upper 128MB get aliased with contents of the lower 88*c2e49f70SReinhard Arlt * 128MB); normally this define should be used for devices with real 32-bit 89*c2e49f70SReinhard Arlt * data path. 90*c2e49f70SReinhard Arlt */ 91*c2e49f70SReinhard Arlt #undef CONFIG_DDR_32BIT 92*c2e49f70SReinhard Arlt 93*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 94*c2e49f70SReinhard Arlt #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 95*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 96*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ 97*c2e49f70SReinhard Arlt DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 98*c2e49f70SReinhard Arlt #define CONFIG_DDR_2T_TIMING 99*c2e49f70SReinhard Arlt 100*c2e49f70SReinhard Arlt /* 101*c2e49f70SReinhard Arlt * Manually set up DDR parameters 102*c2e49f70SReinhard Arlt */ 103*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SIZE 512 /* MB */ 104*c2e49f70SReinhard Arlt 105*c2e49f70SReinhard Arlt #if (CONFIG_SYS_DDR_SIZE == 512) 106*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ 107*c2e49f70SReinhard Arlt CSCONFIG_COL_BIT_10 | \ 108*c2e49f70SReinhard Arlt CSCONFIG_BANK_BIT_3) 109*c2e49f70SReinhard Arlt #endif 110*c2e49f70SReinhard Arlt 111*c2e49f70SReinhard Arlt /* 112*c2e49f70SReinhard Arlt * Manually set up DDR parameters 113*c2e49f70SReinhard Arlt */ 114*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_TIMING_0 0x00220802 115*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_TIMING_1 0x39377322 116*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_TIMING_2 0x2f9848ca /* P9-45, tuning? */ 117*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_TIMING_3 0x00000000 118*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuf,no DYN_PWR */ 119*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_MODE 0x07940242 120*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_MODE2 0x00000000 121*c2e49f70SReinhard Arlt /* autocharge,no open page */ 122*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_INTERVAL 0x04060100 123*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SDRAM_CFG 0x63000000 124*c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SDRAM_CFG2 0x04061000 125*c2e49f70SReinhard Arlt 126*c2e49f70SReinhard Arlt /* 127*c2e49f70SReinhard Arlt * FLASH on the Local Bus 128*c2e49f70SReinhard Arlt */ 129*c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_CFI 130*c2e49f70SReinhard Arlt #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 131*c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 132*c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 133*c2e49f70SReinhard Arlt /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 134*c2e49f70SReinhard Arlt 135*c2e49f70SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 136*c2e49f70SReinhard Arlt (2 << BR_PS_SHIFT) | /* 32bit */ \ 137*c2e49f70SReinhard Arlt BR_V) /* valid */ 138*c2e49f70SReinhard Arlt 139*c2e49f70SReinhard Arlt #define CONFIG_SYS_OR0_PRELIM 0xF8006FF7 /* 128 MB flash size */ 140*c2e49f70SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 141*c2e49f70SReinhard Arlt #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001A /* 128 MB window size */ 142*c2e49f70SReinhard Arlt 143*c2e49f70SReinhard Arlt #define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801) 144*c2e49f70SReinhard Arlt #define CONFIG_SYS_OR1_PRELIM (0xffff8000 | 0x00000200) 145*c2e49f70SReinhard Arlt #define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000 146*c2e49f70SReinhard Arlt #define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x0000000e) 147*c2e49f70SReinhard Arlt 148*c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 149*c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 150*c2e49f70SReinhard Arlt 151*c2e49f70SReinhard Arlt #undef CONFIG_SYS_FLASH_CHECKSUM 152*c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 153*c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 154*c2e49f70SReinhard Arlt 155*c2e49f70SReinhard Arlt #define CONFIG_SYS_MID_FLASH_JUMP 0x7F000000 156*c2e49f70SReinhard Arlt #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 157*c2e49f70SReinhard Arlt 158*c2e49f70SReinhard Arlt #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 159*c2e49f70SReinhard Arlt #define CONFIG_SYS_RAMBOOT 160*c2e49f70SReinhard Arlt #else 161*c2e49f70SReinhard Arlt #undef CONFIG_SYS_RAMBOOT 162*c2e49f70SReinhard Arlt #endif 163*c2e49f70SReinhard Arlt 164*c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_LOCK 1 165*c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 166*c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_END 0x1000 /* size */ 167*c2e49f70SReinhard Arlt 168*c2e49f70SReinhard Arlt #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* size init data */ 169*c2e49f70SReinhard Arlt #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ 170*c2e49f70SReinhard Arlt CONFIG_SYS_GBL_DATA_SIZE) 171*c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 172*c2e49f70SReinhard Arlt 173*c2e49f70SReinhard Arlt #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 174*c2e49f70SReinhard Arlt #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Malloc size */ 175*c2e49f70SReinhard Arlt 176*c2e49f70SReinhard Arlt /* 177*c2e49f70SReinhard Arlt * Local Bus LCRR and LBCR regs 178*c2e49f70SReinhard Arlt * LCRR: DLL bypass, Clock divider is 4 179*c2e49f70SReinhard Arlt * External Local Bus rate is 180*c2e49f70SReinhard Arlt * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 181*c2e49f70SReinhard Arlt */ 182*c2e49f70SReinhard Arlt #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) 183*c2e49f70SReinhard Arlt #define CONFIG_SYS_LBC_LBCR 0x00000000 184*c2e49f70SReinhard Arlt 185*c2e49f70SReinhard Arlt #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 186*c2e49f70SReinhard Arlt 187*c2e49f70SReinhard Arlt /* 188*c2e49f70SReinhard Arlt * Serial Port 189*c2e49f70SReinhard Arlt */ 190*c2e49f70SReinhard Arlt #define CONFIG_CONS_INDEX 1 191*c2e49f70SReinhard Arlt #undef CONFIG_SERIAL_SOFTWARE_FIFO 192*c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550 193*c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_SERIAL 194*c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_REG_SIZE 1 195*c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 196*c2e49f70SReinhard Arlt 197*c2e49f70SReinhard Arlt #define CONFIG_SYS_BAUDRATE_TABLE \ 198*c2e49f70SReinhard Arlt {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 199*c2e49f70SReinhard Arlt 200*c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 201*c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 202*c2e49f70SReinhard Arlt 203*c2e49f70SReinhard Arlt #define CONFIG_CMDLINE_EDITING /* add command line history */ 204*c2e49f70SReinhard Arlt /* Use the HUSH parser */ 205*c2e49f70SReinhard Arlt #define CONFIG_SYS_HUSH_PARSER 206*c2e49f70SReinhard Arlt #ifdef CONFIG_SYS_HUSH_PARSER 207*c2e49f70SReinhard Arlt #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 208*c2e49f70SReinhard Arlt #endif 209*c2e49f70SReinhard Arlt 210*c2e49f70SReinhard Arlt /* pass open firmware flat tree */ 211*c2e49f70SReinhard Arlt #define CONFIG_OF_LIBFDT 212*c2e49f70SReinhard Arlt #define CONFIG_OF_BOARD_SETUP 213*c2e49f70SReinhard Arlt #define CONFIG_OF_STDOUT_VIA_ALIAS 214*c2e49f70SReinhard Arlt 215*c2e49f70SReinhard Arlt /* I2C */ 216*c2e49f70SReinhard Arlt #define CONFIG_I2C_MULTI_BUS 217*c2e49f70SReinhard Arlt #define CONFIG_HARD_I2C /* I2C with hardware support*/ 218*c2e49f70SReinhard Arlt #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 219*c2e49f70SReinhard Arlt #define CONFIG_FSL_I2C 220*c2e49f70SReinhard Arlt #define CONFIG_I2C_CMD_TREE 221*c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 222*c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_SLAVE 0x7F 223*c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_NOPROBES {{0, 0x69}} /* Don't probe these addrs */ 224*c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C1_OFFSET 0x3000 225*c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C2_OFFSET 0x3100 226*c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET 227*c2e49f70SReinhard Arlt /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ 228*c2e49f70SReinhard Arlt 229*c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 230*c2e49f70SReinhard Arlt 231*c2e49f70SReinhard Arlt /* TSEC */ 232*c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1_OFFSET 0x24000 233*c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 234*c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2_OFFSET 0x25000 235*c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 236*c2e49f70SReinhard Arlt 237*c2e49f70SReinhard Arlt /* 238*c2e49f70SReinhard Arlt * General PCI 239*c2e49f70SReinhard Arlt * Addresses are mapped 1-1. 240*c2e49f70SReinhard Arlt */ 241*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 242*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 243*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 244*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 245*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 246*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 247*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 248*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 249*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 250*c2e49f70SReinhard Arlt 251*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 252*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 253*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 254*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 255*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 256*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 257*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 258*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 259*c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 260*c2e49f70SReinhard Arlt 261*c2e49f70SReinhard Arlt #if defined(CONFIG_PCI) 262*c2e49f70SReinhard Arlt 263*c2e49f70SReinhard Arlt #define PCI_64BIT 264*c2e49f70SReinhard Arlt #define PCI_ONE_PCI1 265*c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 266*c2e49f70SReinhard Arlt #undef PCI_ALL_PCI1 267*c2e49f70SReinhard Arlt #undef PCI_TWO_PCI1 268*c2e49f70SReinhard Arlt #undef PCI_ONE_PCI1 269*c2e49f70SReinhard Arlt #endif 270*c2e49f70SReinhard Arlt 271*c2e49f70SReinhard Arlt #define CONFIG_PCI_PNP /* do pci plug-and-play */ 272*c2e49f70SReinhard Arlt #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 273*c2e49f70SReinhard Arlt 274*c2e49f70SReinhard Arlt #define CONFIG_NET_MULTI 275*c2e49f70SReinhard Arlt 276*c2e49f70SReinhard Arlt #undef CONFIG_EEPRO100 277*c2e49f70SReinhard Arlt #undef CONFIG_TULIP 278*c2e49f70SReinhard Arlt 279*c2e49f70SReinhard Arlt #if !defined(CONFIG_PCI_PNP) 280*c2e49f70SReinhard Arlt #define PCI_ENET0_IOADDR 0xFIXME 281*c2e49f70SReinhard Arlt #define PCI_ENET0_MEMADDR 0xFIXME 282*c2e49f70SReinhard Arlt #define PCI_IDSEL_NUMBER 0xFIXME 283*c2e49f70SReinhard Arlt #endif 284*c2e49f70SReinhard Arlt 285*c2e49f70SReinhard Arlt #endif /* CONFIG_PCI */ 286*c2e49f70SReinhard Arlt 287*c2e49f70SReinhard Arlt /* 288*c2e49f70SReinhard Arlt * TSEC configuration 289*c2e49f70SReinhard Arlt */ 290*c2e49f70SReinhard Arlt #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 291*c2e49f70SReinhard Arlt 292*c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 293*c2e49f70SReinhard Arlt #ifndef CONFIG_NET_MULTI 294*c2e49f70SReinhard Arlt #define CONFIG_NET_MULTI 295*c2e49f70SReinhard Arlt #endif 296*c2e49f70SReinhard Arlt 297*c2e49f70SReinhard Arlt #define CONFIG_GMII /* MII PHY management */ 298*c2e49f70SReinhard Arlt #define CONFIG_TSEC1 299*c2e49f70SReinhard Arlt #define CONFIG_TSEC1_NAME "TSEC0" 300*c2e49f70SReinhard Arlt #define CONFIG_TSEC2 301*c2e49f70SReinhard Arlt #define CONFIG_TSEC2_NAME "TSEC1" 302*c2e49f70SReinhard Arlt #define CONFIG_PHY_M88E1111 303*c2e49f70SReinhard Arlt #define TSEC1_PHY_ADDR 0x08 304*c2e49f70SReinhard Arlt #define TSEC2_PHY_ADDR 0x10 305*c2e49f70SReinhard Arlt #define TSEC1_PHYIDX 0 306*c2e49f70SReinhard Arlt #define TSEC2_PHYIDX 0 307*c2e49f70SReinhard Arlt #define TSEC1_FLAGS TSEC_GIGABIT 308*c2e49f70SReinhard Arlt #define TSEC2_FLAGS TSEC_GIGABIT 309*c2e49f70SReinhard Arlt 310*c2e49f70SReinhard Arlt /* Options are: TSEC[0-1] */ 311*c2e49f70SReinhard Arlt #define CONFIG_ETHPRIME "TSEC0" 312*c2e49f70SReinhard Arlt 313*c2e49f70SReinhard Arlt #endif /* CONFIG_TSEC_ENET */ 314*c2e49f70SReinhard Arlt 315*c2e49f70SReinhard Arlt /* 316*c2e49f70SReinhard Arlt * Environment 317*c2e49f70SReinhard Arlt */ 318*c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_RAMBOOT 319*c2e49f70SReinhard Arlt #define CONFIG_ENV_IS_IN_FLASH 320*c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 321*c2e49f70SReinhard Arlt #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 322*c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 323*c2e49f70SReinhard Arlt 324*c2e49f70SReinhard Arlt /* Address and size of Redundant Environment Sector */ 325*c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 326*c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 327*c2e49f70SReinhard Arlt 328*c2e49f70SReinhard Arlt #else 329*c2e49f70SReinhard Arlt #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 330*c2e49f70SReinhard Arlt #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 331*c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 332*c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 333*c2e49f70SReinhard Arlt #endif 334*c2e49f70SReinhard Arlt 335*c2e49f70SReinhard Arlt #define CONFIG_LOADS_ECHO /* echo on for serial download */ 336*c2e49f70SReinhard Arlt #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 337*c2e49f70SReinhard Arlt 338*c2e49f70SReinhard Arlt /* 339*c2e49f70SReinhard Arlt * BOOTP options 340*c2e49f70SReinhard Arlt */ 341*c2e49f70SReinhard Arlt #define CONFIG_BOOTP_BOOTFILESIZE 342*c2e49f70SReinhard Arlt #define CONFIG_BOOTP_BOOTPATH 343*c2e49f70SReinhard Arlt #define CONFIG_BOOTP_GATEWAY 344*c2e49f70SReinhard Arlt #define CONFIG_BOOTP_HOSTNAME 345*c2e49f70SReinhard Arlt 346*c2e49f70SReinhard Arlt /* 347*c2e49f70SReinhard Arlt * Command line configuration. 348*c2e49f70SReinhard Arlt */ 349*c2e49f70SReinhard Arlt #include <config_cmd_default.h> 350*c2e49f70SReinhard Arlt 351*c2e49f70SReinhard Arlt #define CONFIG_CMD_I2C 352*c2e49f70SReinhard Arlt #define CONFIG_CMD_MII 353*c2e49f70SReinhard Arlt #define CONFIG_CMD_PING 354*c2e49f70SReinhard Arlt #define CONFIG_CMD_DATE 355*c2e49f70SReinhard Arlt #define CONFIG_SYS_RTC_BUS_NUM 0x01 356*c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_RTC_ADDR 0x32 357*c2e49f70SReinhard Arlt #define CONFIG_RTC_RX8025 358*c2e49f70SReinhard Arlt #define CONFIG_CMD_TSI148 359*c2e49f70SReinhard Arlt 360*c2e49f70SReinhard Arlt #if defined(CONFIG_PCI) 361*c2e49f70SReinhard Arlt #define CONFIG_CMD_PCI 362*c2e49f70SReinhard Arlt #endif 363*c2e49f70SReinhard Arlt 364*c2e49f70SReinhard Arlt #if defined(CONFIG_SYS_RAMBOOT) 365*c2e49f70SReinhard Arlt #undef CONFIG_CMD_ENV 366*c2e49f70SReinhard Arlt #undef CONFIG_CMD_LOADS 367*c2e49f70SReinhard Arlt #endif 368*c2e49f70SReinhard Arlt 369*c2e49f70SReinhard Arlt #define CONFIG_CMD_ELF 370*c2e49f70SReinhard Arlt /* Pass Ethernet MAC to VxWorks */ 371*c2e49f70SReinhard Arlt #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 372*c2e49f70SReinhard Arlt 373*c2e49f70SReinhard Arlt #undef CONFIG_WATCHDOG /* watchdog disabled */ 374*c2e49f70SReinhard Arlt 375*c2e49f70SReinhard Arlt /* 376*c2e49f70SReinhard Arlt * Miscellaneous configurable options 377*c2e49f70SReinhard Arlt */ 378*c2e49f70SReinhard Arlt #define CONFIG_SYS_LONGHELP /* undef to save memory */ 379*c2e49f70SReinhard Arlt #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 380*c2e49f70SReinhard Arlt #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 381*c2e49f70SReinhard Arlt 382*c2e49f70SReinhard Arlt #if defined(CONFIG_CMD_KGDB) 383*c2e49f70SReinhard Arlt #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 384*c2e49f70SReinhard Arlt #else 385*c2e49f70SReinhard Arlt #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 386*c2e49f70SReinhard Arlt #endif 387*c2e49f70SReinhard Arlt 388*c2e49f70SReinhard Arlt #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 389*c2e49f70SReinhard Arlt #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ 390*c2e49f70SReinhard Arlt #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ 391*c2e49f70SReinhard Arlt #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 392*c2e49f70SReinhard Arlt 393*c2e49f70SReinhard Arlt /* 394*c2e49f70SReinhard Arlt * For booting Linux, the board info and command line data 395*c2e49f70SReinhard Arlt * have to be in the first 8 MB of memory, since this is 396*c2e49f70SReinhard Arlt * the maximum mapped by the Linux kernel during initialization. 397*c2e49f70SReinhard Arlt */ 398*c2e49f70SReinhard Arlt #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init Memory map for Linux*/ 399*c2e49f70SReinhard Arlt 400*c2e49f70SReinhard Arlt #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 401*c2e49f70SReinhard Arlt 402*c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_LOW (\ 403*c2e49f70SReinhard Arlt HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 404*c2e49f70SReinhard Arlt HRCWL_DDR_TO_SCB_CLK_1X1 |\ 405*c2e49f70SReinhard Arlt HRCWL_CSB_TO_CLKIN |\ 406*c2e49f70SReinhard Arlt HRCWL_VCO_1X2 |\ 407*c2e49f70SReinhard Arlt HRCWL_CORE_TO_CSB_2X1) 408*c2e49f70SReinhard Arlt 409*c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 410*c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 411*c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 412*c2e49f70SReinhard Arlt HRCWH_64_BIT_PCI |\ 413*c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 414*c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_DISABLE |\ 415*c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 416*c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 417*c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 418*c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 419*c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 420*c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 421*c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 422*c2e49f70SReinhard Arlt #else 423*c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 424*c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 425*c2e49f70SReinhard Arlt HRCWH_32_BIT_PCI |\ 426*c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 427*c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_ENABLE |\ 428*c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 429*c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 430*c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 431*c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 432*c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 433*c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 434*c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 435*c2e49f70SReinhard Arlt #endif 436*c2e49f70SReinhard Arlt 437*c2e49f70SReinhard Arlt /* System IO Config */ 438*c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRH 0 439*c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRL SICRL_LDP_A 440*c2e49f70SReinhard Arlt 441*c2e49f70SReinhard Arlt #define CONFIG_SYS_HID0_INIT 0x000000000 442*c2e49f70SReinhard Arlt #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK 443*c2e49f70SReinhard Arlt 444*c2e49f70SReinhard Arlt #define CONFIG_SYS_HID2 HID2_HBE 445*c2e49f70SReinhard Arlt 446*c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_PRELIM 447*c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DIR 0x00100000 448*c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DAT 0x00100000 449*c2e49f70SReinhard Arlt 450*c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_PRELIM 451*c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DIR 0x78900000 452*c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DAT 0x70100000 453*c2e49f70SReinhard Arlt 454*c2e49f70SReinhard Arlt #define CONFIG_HIGH_BATS /* High BATs supported */ 455*c2e49f70SReinhard Arlt 456*c2e49f70SReinhard Arlt /* DDR @ 0x00000000 */ 457*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ 458*c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 459*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 460*c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 461*c2e49f70SReinhard Arlt 462*c2e49f70SReinhard Arlt /* PCI @ 0x80000000 */ 463*c2e49f70SReinhard Arlt #ifdef CONFIG_PCI 464*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \ 465*c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 466*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 467*c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 468*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \ 469*c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 470*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 471*c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 472*c2e49f70SReinhard Arlt #else 473*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1L (0) 474*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (0) 475*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2L (0) 476*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (0) 477*c2e49f70SReinhard Arlt #endif 478*c2e49f70SReinhard Arlt 479*c2e49f70SReinhard Arlt #ifdef CONFIG_MPC83XX_PCI2 480*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \ 481*c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 482*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 483*c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 484*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \ 485*c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 486*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 487*c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 488*c2e49f70SReinhard Arlt #else 489*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3L (0) 490*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (0) 491*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4L (0) 492*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (0) 493*c2e49f70SReinhard Arlt #endif 494*c2e49f70SReinhard Arlt 495*c2e49f70SReinhard Arlt /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 496*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 497*c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 498*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 499*c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 500*c2e49f70SReinhard Arlt 501*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) 502*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 503*c2e49f70SReinhard Arlt 504*c2e49f70SReinhard Arlt #if (CONFIG_SYS_DDR_SIZE == 512) 505*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 506*c2e49f70SReinhard Arlt BATL_PP_10 | BATL_MEMCOHERENCE) 507*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 508*c2e49f70SReinhard Arlt BATU_BL_256M | BATU_VS | BATU_VP) 509*c2e49f70SReinhard Arlt #else 510*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (0) 511*c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (0) 512*c2e49f70SReinhard Arlt #endif 513*c2e49f70SReinhard Arlt 514*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 515*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 516*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 517*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 518*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 519*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 520*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 521*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 522*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 523*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 524*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 525*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 526*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 527*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 528*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 529*c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 530*c2e49f70SReinhard Arlt 531*c2e49f70SReinhard Arlt /* 532*c2e49f70SReinhard Arlt * Internal Definitions 533*c2e49f70SReinhard Arlt * 534*c2e49f70SReinhard Arlt * Boot Flags 535*c2e49f70SReinhard Arlt */ 536*c2e49f70SReinhard Arlt #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 537*c2e49f70SReinhard Arlt #define BOOTFLAG_WARM 0x02 /* Software reboot */ 538*c2e49f70SReinhard Arlt 539*c2e49f70SReinhard Arlt #if defined(CONFIG_CMD_KGDB) 540*c2e49f70SReinhard Arlt #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 541*c2e49f70SReinhard Arlt #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 542*c2e49f70SReinhard Arlt #endif 543*c2e49f70SReinhard Arlt 544*c2e49f70SReinhard Arlt /* 545*c2e49f70SReinhard Arlt * Environment Configuration 546*c2e49f70SReinhard Arlt */ 547*c2e49f70SReinhard Arlt #define CONFIG_ENV_OVERWRITE 548*c2e49f70SReinhard Arlt 549*c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 550*c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH0 551*c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH1 552*c2e49f70SReinhard Arlt #endif 553*c2e49f70SReinhard Arlt 554*c2e49f70SReinhard Arlt #define CONFIG_HOSTNAME VME8349 555*c2e49f70SReinhard Arlt #define CONFIG_ROOTPATH /tftpboot/rootfs 556*c2e49f70SReinhard Arlt #define CONFIG_BOOTFILE uImage 557*c2e49f70SReinhard Arlt 558*c2e49f70SReinhard Arlt #define CONFIG_LOADADDR 500000 /* def location for tftp and bootm */ 559*c2e49f70SReinhard Arlt 560*c2e49f70SReinhard Arlt #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 561*c2e49f70SReinhard Arlt #undef CONFIG_BOOTARGS /* boot command will set bootargs */ 562*c2e49f70SReinhard Arlt 563*c2e49f70SReinhard Arlt #define CONFIG_BAUDRATE 115200 564*c2e49f70SReinhard Arlt 565*c2e49f70SReinhard Arlt #define CONFIG_EXTRA_ENV_SETTINGS \ 566*c2e49f70SReinhard Arlt "netdev=eth0\0" \ 567*c2e49f70SReinhard Arlt "hostname=vme8349\0" \ 568*c2e49f70SReinhard Arlt "nfsargs=setenv bootargs root=/dev/nfs rw " \ 569*c2e49f70SReinhard Arlt "nfsroot=${serverip}:${rootpath}\0" \ 570*c2e49f70SReinhard Arlt "ramargs=setenv bootargs root=/dev/ram rw\0" \ 571*c2e49f70SReinhard Arlt "addip=setenv bootargs ${bootargs} " \ 572*c2e49f70SReinhard Arlt "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 573*c2e49f70SReinhard Arlt ":${hostname}:${netdev}:off panic=1\0" \ 574*c2e49f70SReinhard Arlt "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 575*c2e49f70SReinhard Arlt "flash_nfs=run nfsargs addip addtty;" \ 576*c2e49f70SReinhard Arlt "bootm ${kernel_addr}\0" \ 577*c2e49f70SReinhard Arlt "flash_self=run ramargs addip addtty;" \ 578*c2e49f70SReinhard Arlt "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 579*c2e49f70SReinhard Arlt "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 580*c2e49f70SReinhard Arlt "bootm\0" \ 581*c2e49f70SReinhard Arlt "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 582*c2e49f70SReinhard Arlt "update=protect off fff00000 fff3ffff; " \ 583*c2e49f70SReinhard Arlt "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 584*c2e49f70SReinhard Arlt "upd=run load update\0" \ 585*c2e49f70SReinhard Arlt "fdtaddr=400000\0" \ 586*c2e49f70SReinhard Arlt "fdtfile=vme8349.dtb\0" \ 587*c2e49f70SReinhard Arlt "" 588*c2e49f70SReinhard Arlt 589*c2e49f70SReinhard Arlt #define CONFIG_NFSBOOTCOMMAND \ 590*c2e49f70SReinhard Arlt "setenv bootargs root=/dev/nfs rw " \ 591*c2e49f70SReinhard Arlt "nfsroot=$serverip:$rootpath " \ 592*c2e49f70SReinhard Arlt "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 593*c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 594*c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 595*c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 596*c2e49f70SReinhard Arlt "bootm $loadaddr - $fdtaddr" 597*c2e49f70SReinhard Arlt 598*c2e49f70SReinhard Arlt #define CONFIG_RAMBOOTCOMMAND \ 599*c2e49f70SReinhard Arlt "setenv bootargs root=/dev/ram rw " \ 600*c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 601*c2e49f70SReinhard Arlt "tftp $ramdiskaddr $ramdiskfile;" \ 602*c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 603*c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 604*c2e49f70SReinhard Arlt "bootm $loadaddr $ramdiskaddr $fdtaddr" 605*c2e49f70SReinhard Arlt 606*c2e49f70SReinhard Arlt #define CONFIG_BOOTCOMMAND "run flash_self" 607*c2e49f70SReinhard Arlt 608*c2e49f70SReinhard Arlt #endif /* __CONFIG_H */ 609