1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2c2e49f70SReinhard Arlt /* 3c2e49f70SReinhard Arlt * esd vme8349 U-Boot configuration file 4c2e49f70SReinhard Arlt * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 5c2e49f70SReinhard Arlt * 62ae18241SWolfgang Denk * (C) Copyright 2006-2010 7c2e49f70SReinhard Arlt * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8c2e49f70SReinhard Arlt * 9c2e49f70SReinhard Arlt * reinhard.arlt@esd-electronics.de 10c2e49f70SReinhard Arlt * Based on the MPC8349EMDS config. 11c2e49f70SReinhard Arlt */ 12c2e49f70SReinhard Arlt 13c2e49f70SReinhard Arlt /* 14c2e49f70SReinhard Arlt * vme8349 board configuration file. 15c2e49f70SReinhard Arlt */ 16c2e49f70SReinhard Arlt 17c2e49f70SReinhard Arlt #ifndef __CONFIG_H 18c2e49f70SReinhard Arlt #define __CONFIG_H 19c2e49f70SReinhard Arlt 20c2e49f70SReinhard Arlt /* 211dee9be6SReinhard Arlt * Top level Makefile configuration choices 221dee9be6SReinhard Arlt */ 232ae18241SWolfgang Denk #ifdef CONFIG_CADDY2 241dee9be6SReinhard Arlt #define VME_CADDY2 251dee9be6SReinhard Arlt #endif 261dee9be6SReinhard Arlt 271dee9be6SReinhard Arlt /* 28c2e49f70SReinhard Arlt * High Level Configuration Options 29c2e49f70SReinhard Arlt */ 30c2e49f70SReinhard Arlt #define CONFIG_E300 1 /* E300 Family */ 31c2e49f70SReinhard Arlt #define CONFIG_MPC834x 1 /* MPC834x family */ 32c2e49f70SReinhard Arlt #define CONFIG_MPC8349 1 /* MPC8349 specific */ 33c2e49f70SReinhard Arlt #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 34c2e49f70SReinhard Arlt 351dee9be6SReinhard Arlt #define CONFIG_MISC_INIT_R 361dee9be6SReinhard Arlt 37c2e49f70SReinhard Arlt /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 38c2e49f70SReinhard Arlt #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 39c2e49f70SReinhard Arlt 402ae18241SWolfgang Denk #define CONFIG_PCI_66M 412ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 42c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 43c2e49f70SReinhard Arlt #else 44c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 45c2e49f70SReinhard Arlt #endif 46c2e49f70SReinhard Arlt 47c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_CLK_FREQ 482ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 49c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 66000000 50c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 51c2e49f70SReinhard Arlt #else 52c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 33000000 53c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 54c2e49f70SReinhard Arlt #endif 55c2e49f70SReinhard Arlt #endif 56c2e49f70SReinhard Arlt 57c2e49f70SReinhard Arlt #define CONFIG_SYS_IMMR 0xE0000000 58c2e49f70SReinhard Arlt 59c2e49f70SReinhard Arlt #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 60c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 61c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_END 0x00100000 62c2e49f70SReinhard Arlt 63c2e49f70SReinhard Arlt /* 64c2e49f70SReinhard Arlt * DDR Setup 65c2e49f70SReinhard Arlt */ 66c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC /* only for ECC DDR module */ 67c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 681dee9be6SReinhard Arlt #define CONFIG_SPD_EEPROM 691dee9be6SReinhard Arlt #define SPD_EEPROM_ADDRESS 0x54 701dee9be6SReinhard Arlt #define CONFIG_SYS_READ_SPD vme8349_read_spd 71c2e49f70SReinhard Arlt #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 72c2e49f70SReinhard Arlt 73c2e49f70SReinhard Arlt /* 74c2e49f70SReinhard Arlt * 32-bit data path mode. 75c2e49f70SReinhard Arlt * 76c2e49f70SReinhard Arlt * Please note that using this mode for devices with the real density of 64-bit 77c2e49f70SReinhard Arlt * effectively reduces the amount of available memory due to the effect of 78c2e49f70SReinhard Arlt * wrapping around while translating address to row/columns, for example in the 79c2e49f70SReinhard Arlt * 256MB module the upper 128MB get aliased with contents of the lower 80c2e49f70SReinhard Arlt * 128MB); normally this define should be used for devices with real 32-bit 81c2e49f70SReinhard Arlt * data path. 82c2e49f70SReinhard Arlt */ 83c2e49f70SReinhard Arlt #undef CONFIG_DDR_32BIT 84c2e49f70SReinhard Arlt 85c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 86c2e49f70SReinhard Arlt #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 87c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 882fef4020SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 892fef4020SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 90c2e49f70SReinhard Arlt #define CONFIG_DDR_2T_TIMING 912fef4020SJoe Hershberger #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 922fef4020SJoe Hershberger | DDRCDR_ODT \ 932fef4020SJoe Hershberger | DDRCDR_Q_DRN) 942fef4020SJoe Hershberger /* 0x80080001 */ 95c2e49f70SReinhard Arlt 96c2e49f70SReinhard Arlt /* 97c2e49f70SReinhard Arlt * FLASH on the Local Bus 98c2e49f70SReinhard Arlt */ 99c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_CFI 100c2e49f70SReinhard Arlt #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1011dee9be6SReinhard Arlt #ifdef VME_CADDY2 1021dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 1031dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 104c2e49f70SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1057d6a0982SJoe Hershberger BR_PS_16 | /* 16bit */ \ 1067d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 107c2e49f70SReinhard Arlt BR_V) /* valid */ 108c2e49f70SReinhard Arlt 1097d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 1107d6a0982SJoe Hershberger | OR_GPCM_XAM \ 1117d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 1127d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 1137d6a0982SJoe Hershberger | OR_GPCM_XACS \ 1147d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 1157d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 1167d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 1177d6a0982SJoe Hershberger | OR_GPCM_EAD) 1187d6a0982SJoe Hershberger /* 0xffc06ff7 */ 119c2e49f70SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1207d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) 1211dee9be6SReinhard Arlt #else 1221dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 1231dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 1241dee9be6SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1257d6a0982SJoe Hershberger BR_PS_16 | /* 16bit */ \ 1267d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 1271dee9be6SReinhard Arlt BR_V) /* valid */ 1281dee9be6SReinhard Arlt 1297d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 1307d6a0982SJoe Hershberger | OR_GPCM_XAM \ 1317d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 1327d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 1337d6a0982SJoe Hershberger | OR_GPCM_XACS \ 1347d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 1357d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 1367d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 1377d6a0982SJoe Hershberger | OR_GPCM_EAD) 1387d6a0982SJoe Hershberger /* 0xf8006ff7 */ 1391dee9be6SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1407d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 1411dee9be6SReinhard Arlt #endif 1421dee9be6SReinhard Arlt /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 143c2e49f70SReinhard Arlt 1447d6a0982SJoe Hershberger #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 1457d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ 1467d6a0982SJoe Hershberger | BR_PS_32 \ 1477d6a0982SJoe Hershberger | BR_MS_GPCM \ 1487d6a0982SJoe Hershberger | BR_V) 1497d6a0982SJoe Hershberger /* 0xF0001801 */ 1507d6a0982SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ 1517d6a0982SJoe Hershberger | OR_GPCM_SETA) 1527d6a0982SJoe Hershberger /* 0xfffc0208 */ 1537d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE 1547d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) 155c2e49f70SReinhard Arlt 156c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 157c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 158c2e49f70SReinhard Arlt 159c2e49f70SReinhard Arlt #undef CONFIG_SYS_FLASH_CHECKSUM 160c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 161c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 162c2e49f70SReinhard Arlt 16314d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 164c2e49f70SReinhard Arlt 165c2e49f70SReinhard Arlt #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 166c2e49f70SReinhard Arlt #define CONFIG_SYS_RAMBOOT 167c2e49f70SReinhard Arlt #else 168c2e49f70SReinhard Arlt #undef CONFIG_SYS_RAMBOOT 169c2e49f70SReinhard Arlt #endif 170c2e49f70SReinhard Arlt 171c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_LOCK 1 172c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 173553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 174c2e49f70SReinhard Arlt 175553f0982SWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 17625ddd1fbSWolfgang Denk GENERATED_GBL_DATA_SIZE) 177c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 178c2e49f70SReinhard Arlt 179c2e49f70SReinhard Arlt #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 180c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ 181c2e49f70SReinhard Arlt 182c2e49f70SReinhard Arlt /* 183c2e49f70SReinhard Arlt * Local Bus LCRR and LBCR regs 1841dee9be6SReinhard Arlt * LCRR: no DLL bypass, Clock divider is 4 185c2e49f70SReinhard Arlt * External Local Bus rate is 186c2e49f70SReinhard Arlt * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 187c2e49f70SReinhard Arlt */ 188c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 189c2e49f70SReinhard Arlt #define CONFIG_SYS_LBC_LBCR 0x00000000 190c2e49f70SReinhard Arlt 191c2e49f70SReinhard Arlt #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 192c2e49f70SReinhard Arlt 193c2e49f70SReinhard Arlt /* 194c2e49f70SReinhard Arlt * Serial Port 195c2e49f70SReinhard Arlt */ 196c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_SERIAL 197c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_REG_SIZE 1 198c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 199c2e49f70SReinhard Arlt 200c2e49f70SReinhard Arlt #define CONFIG_SYS_BAUDRATE_TABLE \ 201c2e49f70SReinhard Arlt {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 202c2e49f70SReinhard Arlt 203c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 204c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 205c2e49f70SReinhard Arlt 206c2e49f70SReinhard Arlt /* I2C */ 20700f792e0SHeiko Schocher #define CONFIG_SYS_I2C 20800f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 20900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 21000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 21100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 21200f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 21300f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 21400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 21500f792e0SHeiko Schocher #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 216efaf6f1bSPaul Gortmaker /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 217c2e49f70SReinhard Arlt 218c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 219c2e49f70SReinhard Arlt 220c2e49f70SReinhard Arlt /* TSEC */ 221c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1_OFFSET 0x24000 222c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 223c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2_OFFSET 0x25000 224c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 225c2e49f70SReinhard Arlt 226c2e49f70SReinhard Arlt /* 227c2e49f70SReinhard Arlt * General PCI 228c2e49f70SReinhard Arlt * Addresses are mapped 1-1. 229c2e49f70SReinhard Arlt */ 230c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 231c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 232c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 233c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 234c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 235c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 236c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 237c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 238c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 239c2e49f70SReinhard Arlt 240c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 241c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 242c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 243c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 244c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 245c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 246c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 247c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 248c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 249c2e49f70SReinhard Arlt 250c2e49f70SReinhard Arlt #if defined(CONFIG_PCI) 251c2e49f70SReinhard Arlt 252c2e49f70SReinhard Arlt #define PCI_64BIT 253c2e49f70SReinhard Arlt #define PCI_ONE_PCI1 254c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 255c2e49f70SReinhard Arlt #undef PCI_ALL_PCI1 256c2e49f70SReinhard Arlt #undef PCI_TWO_PCI1 257c2e49f70SReinhard Arlt #undef PCI_ONE_PCI1 258c2e49f70SReinhard Arlt #endif 259c2e49f70SReinhard Arlt 2601dee9be6SReinhard Arlt #ifndef VME_CADDY2 2611dee9be6SReinhard Arlt #endif 262c2e49f70SReinhard Arlt 263c2e49f70SReinhard Arlt #undef CONFIG_EEPRO100 264c2e49f70SReinhard Arlt #undef CONFIG_TULIP 265c2e49f70SReinhard Arlt 266c2e49f70SReinhard Arlt #if !defined(CONFIG_PCI_PNP) 267c2e49f70SReinhard Arlt #define PCI_ENET0_IOADDR 0xFIXME 268c2e49f70SReinhard Arlt #define PCI_ENET0_MEMADDR 0xFIXME 269c2e49f70SReinhard Arlt #define PCI_IDSEL_NUMBER 0xFIXME 270c2e49f70SReinhard Arlt #endif 271c2e49f70SReinhard Arlt 2721dee9be6SReinhard Arlt #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 2731dee9be6SReinhard Arlt #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 2741dee9be6SReinhard Arlt 275c2e49f70SReinhard Arlt #endif /* CONFIG_PCI */ 276c2e49f70SReinhard Arlt 277c2e49f70SReinhard Arlt /* 278c2e49f70SReinhard Arlt * TSEC configuration 279c2e49f70SReinhard Arlt */ 280c2e49f70SReinhard Arlt 281c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 282c2e49f70SReinhard Arlt 283c2e49f70SReinhard Arlt #define CONFIG_GMII /* MII PHY management */ 284c2e49f70SReinhard Arlt #define CONFIG_TSEC1 285c2e49f70SReinhard Arlt #define CONFIG_TSEC1_NAME "TSEC0" 286c2e49f70SReinhard Arlt #define CONFIG_TSEC2 287c2e49f70SReinhard Arlt #define CONFIG_TSEC2_NAME "TSEC1" 288c2e49f70SReinhard Arlt #define CONFIG_PHY_M88E1111 289c2e49f70SReinhard Arlt #define TSEC1_PHY_ADDR 0x08 290c2e49f70SReinhard Arlt #define TSEC2_PHY_ADDR 0x10 291c2e49f70SReinhard Arlt #define TSEC1_PHYIDX 0 292c2e49f70SReinhard Arlt #define TSEC2_PHYIDX 0 293c2e49f70SReinhard Arlt #define TSEC1_FLAGS TSEC_GIGABIT 294c2e49f70SReinhard Arlt #define TSEC2_FLAGS TSEC_GIGABIT 295c2e49f70SReinhard Arlt 296c2e49f70SReinhard Arlt /* Options are: TSEC[0-1] */ 297c2e49f70SReinhard Arlt #define CONFIG_ETHPRIME "TSEC0" 298c2e49f70SReinhard Arlt 299c2e49f70SReinhard Arlt #endif /* CONFIG_TSEC_ENET */ 300c2e49f70SReinhard Arlt 301c2e49f70SReinhard Arlt /* 302c2e49f70SReinhard Arlt * Environment 303c2e49f70SReinhard Arlt */ 304c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_RAMBOOT 305c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 306c2e49f70SReinhard Arlt #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 307c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 308c2e49f70SReinhard Arlt 309c2e49f70SReinhard Arlt /* Address and size of Redundant Environment Sector */ 310c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 311c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 312c2e49f70SReinhard Arlt 313c2e49f70SReinhard Arlt #else 314c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 315c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 316c2e49f70SReinhard Arlt #endif 317c2e49f70SReinhard Arlt 318c2e49f70SReinhard Arlt #define CONFIG_LOADS_ECHO /* echo on for serial download */ 319c2e49f70SReinhard Arlt #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 320c2e49f70SReinhard Arlt 321c2e49f70SReinhard Arlt /* 322c2e49f70SReinhard Arlt * BOOTP options 323c2e49f70SReinhard Arlt */ 324c2e49f70SReinhard Arlt #define CONFIG_BOOTP_BOOTFILESIZE 325c2e49f70SReinhard Arlt 326c2e49f70SReinhard Arlt /* 327c2e49f70SReinhard Arlt * Command line configuration. 328c2e49f70SReinhard Arlt */ 329c2e49f70SReinhard Arlt #define CONFIG_SYS_RTC_BUS_NUM 0x01 330c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_RTC_ADDR 0x32 331c2e49f70SReinhard Arlt #define CONFIG_RTC_RX8025 332c2e49f70SReinhard Arlt 333c2e49f70SReinhard Arlt /* Pass Ethernet MAC to VxWorks */ 334c2e49f70SReinhard Arlt #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 335c2e49f70SReinhard Arlt 336c2e49f70SReinhard Arlt #undef CONFIG_WATCHDOG /* watchdog disabled */ 337c2e49f70SReinhard Arlt 338c2e49f70SReinhard Arlt /* 339c2e49f70SReinhard Arlt * Miscellaneous configurable options 340c2e49f70SReinhard Arlt */ 341c2e49f70SReinhard Arlt #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 342c2e49f70SReinhard Arlt 343c2e49f70SReinhard Arlt /* 344c2e49f70SReinhard Arlt * For booting Linux, the board info and command line data 3459f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 346c2e49f70SReinhard Arlt * the maximum mapped by the Linux kernel during initialization. 347c2e49f70SReinhard Arlt */ 3489f530d59SIra W. Snyder #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 349c2e49f70SReinhard Arlt 350c2e49f70SReinhard Arlt #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 351c2e49f70SReinhard Arlt 352c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_LOW (\ 353c2e49f70SReinhard Arlt HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 354c2e49f70SReinhard Arlt HRCWL_DDR_TO_SCB_CLK_1X1 |\ 355c2e49f70SReinhard Arlt HRCWL_CSB_TO_CLKIN |\ 356c2e49f70SReinhard Arlt HRCWL_VCO_1X2 |\ 357c2e49f70SReinhard Arlt HRCWL_CORE_TO_CSB_2X1) 358c2e49f70SReinhard Arlt 359c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 360c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 361c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 362c2e49f70SReinhard Arlt HRCWH_64_BIT_PCI |\ 363c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 364c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_DISABLE |\ 365c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 366c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 367c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 368c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 369c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 370c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 371c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 372c2e49f70SReinhard Arlt #else 373c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 374c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 375c2e49f70SReinhard Arlt HRCWH_32_BIT_PCI |\ 376c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 377c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_ENABLE |\ 378c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 379c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 380c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 381c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 382c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 383c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 384c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 385c2e49f70SReinhard Arlt #endif 386c2e49f70SReinhard Arlt 387c2e49f70SReinhard Arlt /* System IO Config */ 388c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRH 0 389c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRL SICRL_LDP_A 390c2e49f70SReinhard Arlt 391c2e49f70SReinhard Arlt #define CONFIG_SYS_HID0_INIT 0x000000000 3921a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 3931a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE) 394c2e49f70SReinhard Arlt 395c2e49f70SReinhard Arlt #define CONFIG_SYS_HID2 HID2_HBE 396c2e49f70SReinhard Arlt 397c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_PRELIM 398c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DIR 0x00100000 399c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DAT 0x00100000 400c2e49f70SReinhard Arlt 401c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_PRELIM 402c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DIR 0x78900000 403c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DAT 0x70100000 404c2e49f70SReinhard Arlt 405c2e49f70SReinhard Arlt #define CONFIG_HIGH_BATS /* High BATs supported */ 406c2e49f70SReinhard Arlt 407c2e49f70SReinhard Arlt /* DDR @ 0x00000000 */ 40872cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 409c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 410c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 411c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 412c2e49f70SReinhard Arlt 413c2e49f70SReinhard Arlt /* PCI @ 0x80000000 */ 414c2e49f70SReinhard Arlt #ifdef CONFIG_PCI 415842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 41672cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ 417c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 418c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 419c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 42072cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ 421c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 422c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 423c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 424c2e49f70SReinhard Arlt #else 425c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1L (0) 426c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (0) 427c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2L (0) 428c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (0) 429c2e49f70SReinhard Arlt #endif 430c2e49f70SReinhard Arlt 431c2e49f70SReinhard Arlt #ifdef CONFIG_MPC83XX_PCI2 43272cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ 433c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 434c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 435c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 43672cd4087SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ 437c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 438c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 439c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 440c2e49f70SReinhard Arlt #else 441c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3L (0) 442c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (0) 443c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4L (0) 444c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (0) 445c2e49f70SReinhard Arlt #endif 446c2e49f70SReinhard Arlt 447c2e49f70SReinhard Arlt /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 44872cd4087SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 449c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 450c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 451c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 452c2e49f70SReinhard Arlt 45372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) 454c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 455c2e49f70SReinhard Arlt 456c2e49f70SReinhard Arlt #if (CONFIG_SYS_DDR_SIZE == 512) 457c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 45872cd4087SJoe Hershberger BATL_PP_RW | BATL_MEMCOHERENCE) 459c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 460c2e49f70SReinhard Arlt BATU_BL_256M | BATU_VS | BATU_VP) 461c2e49f70SReinhard Arlt #else 462c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (0) 463c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (0) 464c2e49f70SReinhard Arlt #endif 465c2e49f70SReinhard Arlt 466c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 467c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 468c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 469c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 470c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 471c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 472c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 473c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 474c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 475c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 476c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 477c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 478c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 479c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 480c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 481c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 482c2e49f70SReinhard Arlt 483c2e49f70SReinhard Arlt #if defined(CONFIG_CMD_KGDB) 484c2e49f70SReinhard Arlt #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 485c2e49f70SReinhard Arlt #endif 486c2e49f70SReinhard Arlt 487c2e49f70SReinhard Arlt /* 488c2e49f70SReinhard Arlt * Environment Configuration 489c2e49f70SReinhard Arlt */ 490c2e49f70SReinhard Arlt #define CONFIG_ENV_OVERWRITE 491c2e49f70SReinhard Arlt 492c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 493c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH0 494c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH1 495c2e49f70SReinhard Arlt #endif 496c2e49f70SReinhard Arlt 4975bc0543dSMario Six #define CONFIG_HOSTNAME "VME8349" 4988b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/tftpboot/rootfs" 499b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 500c2e49f70SReinhard Arlt 50179f516bcSKim Phillips #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 502c2e49f70SReinhard Arlt 503c2e49f70SReinhard Arlt #define CONFIG_EXTRA_ENV_SETTINGS \ 504c2e49f70SReinhard Arlt "netdev=eth0\0" \ 505c2e49f70SReinhard Arlt "hostname=vme8349\0" \ 506c2e49f70SReinhard Arlt "nfsargs=setenv bootargs root=/dev/nfs rw " \ 507c2e49f70SReinhard Arlt "nfsroot=${serverip}:${rootpath}\0" \ 508c2e49f70SReinhard Arlt "ramargs=setenv bootargs root=/dev/ram rw\0" \ 509c2e49f70SReinhard Arlt "addip=setenv bootargs ${bootargs} " \ 510c2e49f70SReinhard Arlt "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 511c2e49f70SReinhard Arlt ":${hostname}:${netdev}:off panic=1\0" \ 512c2e49f70SReinhard Arlt "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 513c2e49f70SReinhard Arlt "flash_nfs=run nfsargs addip addtty;" \ 514c2e49f70SReinhard Arlt "bootm ${kernel_addr}\0" \ 515c2e49f70SReinhard Arlt "flash_self=run ramargs addip addtty;" \ 516c2e49f70SReinhard Arlt "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 517c2e49f70SReinhard Arlt "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 518c2e49f70SReinhard Arlt "bootm\0" \ 519c2e49f70SReinhard Arlt "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 520c2e49f70SReinhard Arlt "update=protect off fff00000 fff3ffff; " \ 521c2e49f70SReinhard Arlt "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 522c2e49f70SReinhard Arlt "upd=run load update\0" \ 52379f516bcSKim Phillips "fdtaddr=780000\0" \ 524c2e49f70SReinhard Arlt "fdtfile=vme8349.dtb\0" \ 525c2e49f70SReinhard Arlt "" 526c2e49f70SReinhard Arlt 527c2e49f70SReinhard Arlt #define CONFIG_NFSBOOTCOMMAND \ 528c2e49f70SReinhard Arlt "setenv bootargs root=/dev/nfs rw " \ 529c2e49f70SReinhard Arlt "nfsroot=$serverip:$rootpath " \ 530c7357a2bSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 531c7357a2bSJoe Hershberger "$netdev:off " \ 532c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 533c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 534c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 535c2e49f70SReinhard Arlt "bootm $loadaddr - $fdtaddr" 536c2e49f70SReinhard Arlt 537c2e49f70SReinhard Arlt #define CONFIG_RAMBOOTCOMMAND \ 538c2e49f70SReinhard Arlt "setenv bootargs root=/dev/ram rw " \ 539c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 540c2e49f70SReinhard Arlt "tftp $ramdiskaddr $ramdiskfile;" \ 541c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 542c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 543c2e49f70SReinhard Arlt "bootm $loadaddr $ramdiskaddr $fdtaddr" 544c2e49f70SReinhard Arlt 545c2e49f70SReinhard Arlt #define CONFIG_BOOTCOMMAND "run flash_self" 546c2e49f70SReinhard Arlt 5471dee9be6SReinhard Arlt #ifndef __ASSEMBLY__ 5481dee9be6SReinhard Arlt int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 5491dee9be6SReinhard Arlt unsigned char *buffer, int len); 5501dee9be6SReinhard Arlt #endif 5511dee9be6SReinhard Arlt 552c2e49f70SReinhard Arlt #endif /* __CONFIG_H */ 553