1c2e49f70SReinhard Arlt /* 2c2e49f70SReinhard Arlt * esd vme8349 U-Boot configuration file 3c2e49f70SReinhard Arlt * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4c2e49f70SReinhard Arlt * 52ae18241SWolfgang Denk * (C) Copyright 2006-2010 6c2e49f70SReinhard Arlt * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7c2e49f70SReinhard Arlt * 8c2e49f70SReinhard Arlt * reinhard.arlt@esd-electronics.de 9c2e49f70SReinhard Arlt * Based on the MPC8349EMDS config. 10c2e49f70SReinhard Arlt * 111a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 12c2e49f70SReinhard Arlt */ 13c2e49f70SReinhard Arlt 14c2e49f70SReinhard Arlt /* 15c2e49f70SReinhard Arlt * vme8349 board configuration file. 16c2e49f70SReinhard Arlt */ 17c2e49f70SReinhard Arlt 18c2e49f70SReinhard Arlt #ifndef __CONFIG_H 19c2e49f70SReinhard Arlt #define __CONFIG_H 20c2e49f70SReinhard Arlt 21c2e49f70SReinhard Arlt /* 221dee9be6SReinhard Arlt * Top level Makefile configuration choices 231dee9be6SReinhard Arlt */ 242ae18241SWolfgang Denk #ifdef CONFIG_CADDY2 251dee9be6SReinhard Arlt #define VME_CADDY2 261dee9be6SReinhard Arlt #endif 271dee9be6SReinhard Arlt 281dee9be6SReinhard Arlt /* 29c2e49f70SReinhard Arlt * High Level Configuration Options 30c2e49f70SReinhard Arlt */ 31c2e49f70SReinhard Arlt #define CONFIG_E300 1 /* E300 Family */ 32c2e49f70SReinhard Arlt #define CONFIG_MPC834x 1 /* MPC834x family */ 33c2e49f70SReinhard Arlt #define CONFIG_MPC8349 1 /* MPC8349 specific */ 34c2e49f70SReinhard Arlt #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 35c2e49f70SReinhard Arlt 361dee9be6SReinhard Arlt #define CONFIG_MISC_INIT_R 371dee9be6SReinhard Arlt 38c2e49f70SReinhard Arlt /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 39c2e49f70SReinhard Arlt #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 40c2e49f70SReinhard Arlt 412ae18241SWolfgang Denk #define CONFIG_PCI_66M 422ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 43c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 44c2e49f70SReinhard Arlt #else 45c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 46c2e49f70SReinhard Arlt #endif 47c2e49f70SReinhard Arlt 48c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_CLK_FREQ 492ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 50c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 66000000 51c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 52c2e49f70SReinhard Arlt #else 53c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 33000000 54c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 55c2e49f70SReinhard Arlt #endif 56c2e49f70SReinhard Arlt #endif 57c2e49f70SReinhard Arlt 58c2e49f70SReinhard Arlt #define CONFIG_SYS_IMMR 0xE0000000 59c2e49f70SReinhard Arlt 60c2e49f70SReinhard Arlt #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 61c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 62c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_END 0x00100000 63c2e49f70SReinhard Arlt 64c2e49f70SReinhard Arlt /* 65c2e49f70SReinhard Arlt * DDR Setup 66c2e49f70SReinhard Arlt */ 67c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC /* only for ECC DDR module */ 68c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 691dee9be6SReinhard Arlt #define CONFIG_SPD_EEPROM 701dee9be6SReinhard Arlt #define SPD_EEPROM_ADDRESS 0x54 711dee9be6SReinhard Arlt #define CONFIG_SYS_READ_SPD vme8349_read_spd 72c2e49f70SReinhard Arlt #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 73c2e49f70SReinhard Arlt 74c2e49f70SReinhard Arlt /* 75c2e49f70SReinhard Arlt * 32-bit data path mode. 76c2e49f70SReinhard Arlt * 77c2e49f70SReinhard Arlt * Please note that using this mode for devices with the real density of 64-bit 78c2e49f70SReinhard Arlt * effectively reduces the amount of available memory due to the effect of 79c2e49f70SReinhard Arlt * wrapping around while translating address to row/columns, for example in the 80c2e49f70SReinhard Arlt * 256MB module the upper 128MB get aliased with contents of the lower 81c2e49f70SReinhard Arlt * 128MB); normally this define should be used for devices with real 32-bit 82c2e49f70SReinhard Arlt * data path. 83c2e49f70SReinhard Arlt */ 84c2e49f70SReinhard Arlt #undef CONFIG_DDR_32BIT 85c2e49f70SReinhard Arlt 86c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 87c2e49f70SReinhard Arlt #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 88c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 892fef4020SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 902fef4020SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 91c2e49f70SReinhard Arlt #define CONFIG_DDR_2T_TIMING 922fef4020SJoe Hershberger #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 932fef4020SJoe Hershberger | DDRCDR_ODT \ 942fef4020SJoe Hershberger | DDRCDR_Q_DRN) 952fef4020SJoe Hershberger /* 0x80080001 */ 96c2e49f70SReinhard Arlt 97c2e49f70SReinhard Arlt /* 98c2e49f70SReinhard Arlt * FLASH on the Local Bus 99c2e49f70SReinhard Arlt */ 100c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_CFI 101c2e49f70SReinhard Arlt #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1021dee9be6SReinhard Arlt #ifdef VME_CADDY2 1031dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 1041dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 105c2e49f70SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1067d6a0982SJoe Hershberger BR_PS_16 | /* 16bit */ \ 1077d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 108c2e49f70SReinhard Arlt BR_V) /* valid */ 109c2e49f70SReinhard Arlt 1107d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 1117d6a0982SJoe Hershberger | OR_GPCM_XAM \ 1127d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 1137d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 1147d6a0982SJoe Hershberger | OR_GPCM_XACS \ 1157d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 1167d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 1177d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 1187d6a0982SJoe Hershberger | OR_GPCM_EAD) 1197d6a0982SJoe Hershberger /* 0xffc06ff7 */ 120c2e49f70SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1217d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) 1221dee9be6SReinhard Arlt #else 1231dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 1241dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 1251dee9be6SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1267d6a0982SJoe Hershberger BR_PS_16 | /* 16bit */ \ 1277d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 1281dee9be6SReinhard Arlt BR_V) /* valid */ 1291dee9be6SReinhard Arlt 1307d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 1317d6a0982SJoe Hershberger | OR_GPCM_XAM \ 1327d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 1337d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 1347d6a0982SJoe Hershberger | OR_GPCM_XACS \ 1357d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 1367d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 1377d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 1387d6a0982SJoe Hershberger | OR_GPCM_EAD) 1397d6a0982SJoe Hershberger /* 0xf8006ff7 */ 1401dee9be6SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1417d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 1421dee9be6SReinhard Arlt #endif 1431dee9be6SReinhard Arlt /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 144c2e49f70SReinhard Arlt 1457d6a0982SJoe Hershberger #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 1467d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ 1477d6a0982SJoe Hershberger | BR_PS_32 \ 1487d6a0982SJoe Hershberger | BR_MS_GPCM \ 1497d6a0982SJoe Hershberger | BR_V) 1507d6a0982SJoe Hershberger /* 0xF0001801 */ 1517d6a0982SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ 1527d6a0982SJoe Hershberger | OR_GPCM_SETA) 1537d6a0982SJoe Hershberger /* 0xfffc0208 */ 1547d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE 1557d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) 156c2e49f70SReinhard Arlt 157c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 158c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 159c2e49f70SReinhard Arlt 160c2e49f70SReinhard Arlt #undef CONFIG_SYS_FLASH_CHECKSUM 161c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 162c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 163c2e49f70SReinhard Arlt 16414d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 165c2e49f70SReinhard Arlt 166c2e49f70SReinhard Arlt #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 167c2e49f70SReinhard Arlt #define CONFIG_SYS_RAMBOOT 168c2e49f70SReinhard Arlt #else 169c2e49f70SReinhard Arlt #undef CONFIG_SYS_RAMBOOT 170c2e49f70SReinhard Arlt #endif 171c2e49f70SReinhard Arlt 172c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_LOCK 1 173c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 174553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 175c2e49f70SReinhard Arlt 176553f0982SWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 17725ddd1fbSWolfgang Denk GENERATED_GBL_DATA_SIZE) 178c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 179c2e49f70SReinhard Arlt 180c2e49f70SReinhard Arlt #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 181c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ 182c2e49f70SReinhard Arlt 183c2e49f70SReinhard Arlt /* 184c2e49f70SReinhard Arlt * Local Bus LCRR and LBCR regs 1851dee9be6SReinhard Arlt * LCRR: no DLL bypass, Clock divider is 4 186c2e49f70SReinhard Arlt * External Local Bus rate is 187c2e49f70SReinhard Arlt * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 188c2e49f70SReinhard Arlt */ 189c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 190c2e49f70SReinhard Arlt #define CONFIG_SYS_LBC_LBCR 0x00000000 191c2e49f70SReinhard Arlt 192c2e49f70SReinhard Arlt #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 193c2e49f70SReinhard Arlt 194c2e49f70SReinhard Arlt /* 195c2e49f70SReinhard Arlt * Serial Port 196c2e49f70SReinhard Arlt */ 197c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_SERIAL 198c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_REG_SIZE 1 199c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 200c2e49f70SReinhard Arlt 201c2e49f70SReinhard Arlt #define CONFIG_SYS_BAUDRATE_TABLE \ 202c2e49f70SReinhard Arlt {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 203c2e49f70SReinhard Arlt 204c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 205c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 206c2e49f70SReinhard Arlt 207c2e49f70SReinhard Arlt /* I2C */ 20800f792e0SHeiko Schocher #define CONFIG_SYS_I2C 20900f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 21000f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 21100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 21200f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 21300f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 21400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 21500f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 21600f792e0SHeiko Schocher #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 217efaf6f1bSPaul Gortmaker /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 218c2e49f70SReinhard Arlt 219c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 220c2e49f70SReinhard Arlt 221c2e49f70SReinhard Arlt /* TSEC */ 222c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1_OFFSET 0x24000 223c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 224c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2_OFFSET 0x25000 225c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 226c2e49f70SReinhard Arlt 227c2e49f70SReinhard Arlt /* 228c2e49f70SReinhard Arlt * General PCI 229c2e49f70SReinhard Arlt * Addresses are mapped 1-1. 230c2e49f70SReinhard Arlt */ 231c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 232c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 233c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 234c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 235c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 236c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 237c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 238c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 239c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 240c2e49f70SReinhard Arlt 241c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 242c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 243c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 244c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 245c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 246c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 247c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 248c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 249c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 250c2e49f70SReinhard Arlt 251c2e49f70SReinhard Arlt #if defined(CONFIG_PCI) 252c2e49f70SReinhard Arlt 253c2e49f70SReinhard Arlt #define PCI_64BIT 254c2e49f70SReinhard Arlt #define PCI_ONE_PCI1 255c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 256c2e49f70SReinhard Arlt #undef PCI_ALL_PCI1 257c2e49f70SReinhard Arlt #undef PCI_TWO_PCI1 258c2e49f70SReinhard Arlt #undef PCI_ONE_PCI1 259c2e49f70SReinhard Arlt #endif 260c2e49f70SReinhard Arlt 2611dee9be6SReinhard Arlt #ifndef VME_CADDY2 2621dee9be6SReinhard Arlt #endif 263c2e49f70SReinhard Arlt 264c2e49f70SReinhard Arlt #undef CONFIG_EEPRO100 265c2e49f70SReinhard Arlt #undef CONFIG_TULIP 266c2e49f70SReinhard Arlt 267c2e49f70SReinhard Arlt #if !defined(CONFIG_PCI_PNP) 268c2e49f70SReinhard Arlt #define PCI_ENET0_IOADDR 0xFIXME 269c2e49f70SReinhard Arlt #define PCI_ENET0_MEMADDR 0xFIXME 270c2e49f70SReinhard Arlt #define PCI_IDSEL_NUMBER 0xFIXME 271c2e49f70SReinhard Arlt #endif 272c2e49f70SReinhard Arlt 2731dee9be6SReinhard Arlt #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 2741dee9be6SReinhard Arlt #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 2751dee9be6SReinhard Arlt 276c2e49f70SReinhard Arlt #endif /* CONFIG_PCI */ 277c2e49f70SReinhard Arlt 278c2e49f70SReinhard Arlt /* 279c2e49f70SReinhard Arlt * TSEC configuration 280c2e49f70SReinhard Arlt */ 281c2e49f70SReinhard Arlt 282c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 283c2e49f70SReinhard Arlt 284c2e49f70SReinhard Arlt #define CONFIG_GMII /* MII PHY management */ 285c2e49f70SReinhard Arlt #define CONFIG_TSEC1 286c2e49f70SReinhard Arlt #define CONFIG_TSEC1_NAME "TSEC0" 287c2e49f70SReinhard Arlt #define CONFIG_TSEC2 288c2e49f70SReinhard Arlt #define CONFIG_TSEC2_NAME "TSEC1" 289c2e49f70SReinhard Arlt #define CONFIG_PHY_M88E1111 290c2e49f70SReinhard Arlt #define TSEC1_PHY_ADDR 0x08 291c2e49f70SReinhard Arlt #define TSEC2_PHY_ADDR 0x10 292c2e49f70SReinhard Arlt #define TSEC1_PHYIDX 0 293c2e49f70SReinhard Arlt #define TSEC2_PHYIDX 0 294c2e49f70SReinhard Arlt #define TSEC1_FLAGS TSEC_GIGABIT 295c2e49f70SReinhard Arlt #define TSEC2_FLAGS TSEC_GIGABIT 296c2e49f70SReinhard Arlt 297c2e49f70SReinhard Arlt /* Options are: TSEC[0-1] */ 298c2e49f70SReinhard Arlt #define CONFIG_ETHPRIME "TSEC0" 299c2e49f70SReinhard Arlt 300c2e49f70SReinhard Arlt #endif /* CONFIG_TSEC_ENET */ 301c2e49f70SReinhard Arlt 302c2e49f70SReinhard Arlt /* 303c2e49f70SReinhard Arlt * Environment 304c2e49f70SReinhard Arlt */ 305c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_RAMBOOT 306c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 307c2e49f70SReinhard Arlt #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 308c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 309c2e49f70SReinhard Arlt 310c2e49f70SReinhard Arlt /* Address and size of Redundant Environment Sector */ 311c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 312c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 313c2e49f70SReinhard Arlt 314c2e49f70SReinhard Arlt #else 315c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 316c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 317c2e49f70SReinhard Arlt #endif 318c2e49f70SReinhard Arlt 319c2e49f70SReinhard Arlt #define CONFIG_LOADS_ECHO /* echo on for serial download */ 320c2e49f70SReinhard Arlt #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 321c2e49f70SReinhard Arlt 322c2e49f70SReinhard Arlt /* 323c2e49f70SReinhard Arlt * BOOTP options 324c2e49f70SReinhard Arlt */ 325c2e49f70SReinhard Arlt #define CONFIG_BOOTP_BOOTFILESIZE 326c2e49f70SReinhard Arlt 327c2e49f70SReinhard Arlt /* 328c2e49f70SReinhard Arlt * Command line configuration. 329c2e49f70SReinhard Arlt */ 330c2e49f70SReinhard Arlt #define CONFIG_SYS_RTC_BUS_NUM 0x01 331c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_RTC_ADDR 0x32 332c2e49f70SReinhard Arlt #define CONFIG_RTC_RX8025 333c2e49f70SReinhard Arlt 334c2e49f70SReinhard Arlt /* Pass Ethernet MAC to VxWorks */ 335c2e49f70SReinhard Arlt #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 336c2e49f70SReinhard Arlt 337c2e49f70SReinhard Arlt #undef CONFIG_WATCHDOG /* watchdog disabled */ 338c2e49f70SReinhard Arlt 339c2e49f70SReinhard Arlt /* 340c2e49f70SReinhard Arlt * Miscellaneous configurable options 341c2e49f70SReinhard Arlt */ 342c2e49f70SReinhard Arlt #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 343c2e49f70SReinhard Arlt 344c2e49f70SReinhard Arlt /* 345c2e49f70SReinhard Arlt * For booting Linux, the board info and command line data 3469f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 347c2e49f70SReinhard Arlt * the maximum mapped by the Linux kernel during initialization. 348c2e49f70SReinhard Arlt */ 3499f530d59SIra W. Snyder #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 350c2e49f70SReinhard Arlt 351c2e49f70SReinhard Arlt #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 352c2e49f70SReinhard Arlt 353c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_LOW (\ 354c2e49f70SReinhard Arlt HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 355c2e49f70SReinhard Arlt HRCWL_DDR_TO_SCB_CLK_1X1 |\ 356c2e49f70SReinhard Arlt HRCWL_CSB_TO_CLKIN |\ 357c2e49f70SReinhard Arlt HRCWL_VCO_1X2 |\ 358c2e49f70SReinhard Arlt HRCWL_CORE_TO_CSB_2X1) 359c2e49f70SReinhard Arlt 360c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 361c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 362c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 363c2e49f70SReinhard Arlt HRCWH_64_BIT_PCI |\ 364c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 365c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_DISABLE |\ 366c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 367c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 368c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 369c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 370c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 371c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 372c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 373c2e49f70SReinhard Arlt #else 374c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 375c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 376c2e49f70SReinhard Arlt HRCWH_32_BIT_PCI |\ 377c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 378c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_ENABLE |\ 379c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 380c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 381c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 382c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 383c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 384c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 385c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 386c2e49f70SReinhard Arlt #endif 387c2e49f70SReinhard Arlt 388c2e49f70SReinhard Arlt /* System IO Config */ 389c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRH 0 390c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRL SICRL_LDP_A 391c2e49f70SReinhard Arlt 392c2e49f70SReinhard Arlt #define CONFIG_SYS_HID0_INIT 0x000000000 3931a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 3941a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE) 395c2e49f70SReinhard Arlt 396c2e49f70SReinhard Arlt #define CONFIG_SYS_HID2 HID2_HBE 397c2e49f70SReinhard Arlt 398c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_PRELIM 399c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DIR 0x00100000 400c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DAT 0x00100000 401c2e49f70SReinhard Arlt 402c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_PRELIM 403c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DIR 0x78900000 404c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DAT 0x70100000 405c2e49f70SReinhard Arlt 406c2e49f70SReinhard Arlt #define CONFIG_HIGH_BATS /* High BATs supported */ 407c2e49f70SReinhard Arlt 408c2e49f70SReinhard Arlt /* DDR @ 0x00000000 */ 40972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 410c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 411c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 412c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 413c2e49f70SReinhard Arlt 414c2e49f70SReinhard Arlt /* PCI @ 0x80000000 */ 415c2e49f70SReinhard Arlt #ifdef CONFIG_PCI 416842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 41772cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ 418c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 419c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 420c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 42172cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ 422c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 423c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 424c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 425c2e49f70SReinhard Arlt #else 426c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1L (0) 427c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (0) 428c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2L (0) 429c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (0) 430c2e49f70SReinhard Arlt #endif 431c2e49f70SReinhard Arlt 432c2e49f70SReinhard Arlt #ifdef CONFIG_MPC83XX_PCI2 43372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ 434c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 435c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 436c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 43772cd4087SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ 438c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 439c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 440c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 441c2e49f70SReinhard Arlt #else 442c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3L (0) 443c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (0) 444c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4L (0) 445c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (0) 446c2e49f70SReinhard Arlt #endif 447c2e49f70SReinhard Arlt 448c2e49f70SReinhard Arlt /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 44972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 450c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 451c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 452c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 453c2e49f70SReinhard Arlt 45472cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) 455c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 456c2e49f70SReinhard Arlt 457c2e49f70SReinhard Arlt #if (CONFIG_SYS_DDR_SIZE == 512) 458c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 45972cd4087SJoe Hershberger BATL_PP_RW | BATL_MEMCOHERENCE) 460c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 461c2e49f70SReinhard Arlt BATU_BL_256M | BATU_VS | BATU_VP) 462c2e49f70SReinhard Arlt #else 463c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (0) 464c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (0) 465c2e49f70SReinhard Arlt #endif 466c2e49f70SReinhard Arlt 467c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 468c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 469c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 470c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 471c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 472c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 473c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 474c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 475c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 476c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 477c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 478c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 479c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 480c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 481c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 482c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 483c2e49f70SReinhard Arlt 484c2e49f70SReinhard Arlt #if defined(CONFIG_CMD_KGDB) 485c2e49f70SReinhard Arlt #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 486c2e49f70SReinhard Arlt #endif 487c2e49f70SReinhard Arlt 488c2e49f70SReinhard Arlt /* 489c2e49f70SReinhard Arlt * Environment Configuration 490c2e49f70SReinhard Arlt */ 491c2e49f70SReinhard Arlt #define CONFIG_ENV_OVERWRITE 492c2e49f70SReinhard Arlt 493c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 494c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH0 495c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH1 496c2e49f70SReinhard Arlt #endif 497c2e49f70SReinhard Arlt 498*5bc0543dSMario Six #define CONFIG_HOSTNAME "VME8349" 4998b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/tftpboot/rootfs" 500b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 501c2e49f70SReinhard Arlt 50279f516bcSKim Phillips #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 503c2e49f70SReinhard Arlt 504c2e49f70SReinhard Arlt #define CONFIG_EXTRA_ENV_SETTINGS \ 505c2e49f70SReinhard Arlt "netdev=eth0\0" \ 506c2e49f70SReinhard Arlt "hostname=vme8349\0" \ 507c2e49f70SReinhard Arlt "nfsargs=setenv bootargs root=/dev/nfs rw " \ 508c2e49f70SReinhard Arlt "nfsroot=${serverip}:${rootpath}\0" \ 509c2e49f70SReinhard Arlt "ramargs=setenv bootargs root=/dev/ram rw\0" \ 510c2e49f70SReinhard Arlt "addip=setenv bootargs ${bootargs} " \ 511c2e49f70SReinhard Arlt "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 512c2e49f70SReinhard Arlt ":${hostname}:${netdev}:off panic=1\0" \ 513c2e49f70SReinhard Arlt "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 514c2e49f70SReinhard Arlt "flash_nfs=run nfsargs addip addtty;" \ 515c2e49f70SReinhard Arlt "bootm ${kernel_addr}\0" \ 516c2e49f70SReinhard Arlt "flash_self=run ramargs addip addtty;" \ 517c2e49f70SReinhard Arlt "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 518c2e49f70SReinhard Arlt "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 519c2e49f70SReinhard Arlt "bootm\0" \ 520c2e49f70SReinhard Arlt "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 521c2e49f70SReinhard Arlt "update=protect off fff00000 fff3ffff; " \ 522c2e49f70SReinhard Arlt "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 523c2e49f70SReinhard Arlt "upd=run load update\0" \ 52479f516bcSKim Phillips "fdtaddr=780000\0" \ 525c2e49f70SReinhard Arlt "fdtfile=vme8349.dtb\0" \ 526c2e49f70SReinhard Arlt "" 527c2e49f70SReinhard Arlt 528c2e49f70SReinhard Arlt #define CONFIG_NFSBOOTCOMMAND \ 529c2e49f70SReinhard Arlt "setenv bootargs root=/dev/nfs rw " \ 530c2e49f70SReinhard Arlt "nfsroot=$serverip:$rootpath " \ 531c7357a2bSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 532c7357a2bSJoe Hershberger "$netdev:off " \ 533c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 534c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 535c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 536c2e49f70SReinhard Arlt "bootm $loadaddr - $fdtaddr" 537c2e49f70SReinhard Arlt 538c2e49f70SReinhard Arlt #define CONFIG_RAMBOOTCOMMAND \ 539c2e49f70SReinhard Arlt "setenv bootargs root=/dev/ram rw " \ 540c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 541c2e49f70SReinhard Arlt "tftp $ramdiskaddr $ramdiskfile;" \ 542c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 543c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 544c2e49f70SReinhard Arlt "bootm $loadaddr $ramdiskaddr $fdtaddr" 545c2e49f70SReinhard Arlt 546c2e49f70SReinhard Arlt #define CONFIG_BOOTCOMMAND "run flash_self" 547c2e49f70SReinhard Arlt 5481dee9be6SReinhard Arlt #ifndef __ASSEMBLY__ 5491dee9be6SReinhard Arlt int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 5501dee9be6SReinhard Arlt unsigned char *buffer, int len); 5511dee9be6SReinhard Arlt #endif 5521dee9be6SReinhard Arlt 553c2e49f70SReinhard Arlt #endif /* __CONFIG_H */ 554