1c2e49f70SReinhard Arlt /* 2c2e49f70SReinhard Arlt * esd vme8349 U-Boot configuration file 3c2e49f70SReinhard Arlt * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 4c2e49f70SReinhard Arlt * 52ae18241SWolfgang Denk * (C) Copyright 2006-2010 6c2e49f70SReinhard Arlt * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7c2e49f70SReinhard Arlt * 8c2e49f70SReinhard Arlt * reinhard.arlt@esd-electronics.de 9c2e49f70SReinhard Arlt * Based on the MPC8349EMDS config. 10c2e49f70SReinhard Arlt * 11*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 12c2e49f70SReinhard Arlt */ 13c2e49f70SReinhard Arlt 14c2e49f70SReinhard Arlt /* 15c2e49f70SReinhard Arlt * vme8349 board configuration file. 16c2e49f70SReinhard Arlt */ 17c2e49f70SReinhard Arlt 18c2e49f70SReinhard Arlt #ifndef __CONFIG_H 19c2e49f70SReinhard Arlt #define __CONFIG_H 20c2e49f70SReinhard Arlt 21c2e49f70SReinhard Arlt /* 221dee9be6SReinhard Arlt * Top level Makefile configuration choices 231dee9be6SReinhard Arlt */ 242ae18241SWolfgang Denk #ifdef CONFIG_CADDY2 251dee9be6SReinhard Arlt #define VME_CADDY2 261dee9be6SReinhard Arlt #endif 271dee9be6SReinhard Arlt 281dee9be6SReinhard Arlt /* 29c2e49f70SReinhard Arlt * High Level Configuration Options 30c2e49f70SReinhard Arlt */ 31c2e49f70SReinhard Arlt #define CONFIG_E300 1 /* E300 Family */ 32c2e49f70SReinhard Arlt #define CONFIG_MPC83xx 1 /* MPC83xx family */ 33c2e49f70SReinhard Arlt #define CONFIG_MPC834x 1 /* MPC834x family */ 34c2e49f70SReinhard Arlt #define CONFIG_MPC8349 1 /* MPC8349 specific */ 35c2e49f70SReinhard Arlt #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ 36c2e49f70SReinhard Arlt 372ae18241SWolfgang Denk #define CONFIG_SYS_TEXT_BASE 0xFFF00000 382ae18241SWolfgang Denk 391dee9be6SReinhard Arlt #define CONFIG_MISC_INIT_R 401dee9be6SReinhard Arlt 41c2e49f70SReinhard Arlt #define CONFIG_PCI 42c2e49f70SReinhard Arlt /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 43c2e49f70SReinhard Arlt #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 44c2e49f70SReinhard Arlt 452ae18241SWolfgang Denk #define CONFIG_PCI_66M 462ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 47c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ 48c2e49f70SReinhard Arlt #else 49c2e49f70SReinhard Arlt #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ 50c2e49f70SReinhard Arlt #endif 51c2e49f70SReinhard Arlt 52c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_CLK_FREQ 532ae18241SWolfgang Denk #ifdef CONFIG_PCI_66M 54c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 66000000 55c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 56c2e49f70SReinhard Arlt #else 57c2e49f70SReinhard Arlt #define CONFIG_SYS_CLK_FREQ 33000000 58c2e49f70SReinhard Arlt #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 59c2e49f70SReinhard Arlt #endif 60c2e49f70SReinhard Arlt #endif 61c2e49f70SReinhard Arlt 62c2e49f70SReinhard Arlt #define CONFIG_SYS_IMMR 0xE0000000 63c2e49f70SReinhard Arlt 64c2e49f70SReinhard Arlt #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 65c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ 66c2e49f70SReinhard Arlt #define CONFIG_SYS_MEMTEST_END 0x00100000 67c2e49f70SReinhard Arlt 68c2e49f70SReinhard Arlt /* 69c2e49f70SReinhard Arlt * DDR Setup 70c2e49f70SReinhard Arlt */ 71c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC /* only for ECC DDR module */ 72c2e49f70SReinhard Arlt #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 731dee9be6SReinhard Arlt #define CONFIG_SPD_EEPROM 741dee9be6SReinhard Arlt #define SPD_EEPROM_ADDRESS 0x54 751dee9be6SReinhard Arlt #define CONFIG_SYS_READ_SPD vme8349_read_spd 76c2e49f70SReinhard Arlt #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 77c2e49f70SReinhard Arlt 78c2e49f70SReinhard Arlt /* 79c2e49f70SReinhard Arlt * 32-bit data path mode. 80c2e49f70SReinhard Arlt * 81c2e49f70SReinhard Arlt * Please note that using this mode for devices with the real density of 64-bit 82c2e49f70SReinhard Arlt * effectively reduces the amount of available memory due to the effect of 83c2e49f70SReinhard Arlt * wrapping around while translating address to row/columns, for example in the 84c2e49f70SReinhard Arlt * 256MB module the upper 128MB get aliased with contents of the lower 85c2e49f70SReinhard Arlt * 128MB); normally this define should be used for devices with real 32-bit 86c2e49f70SReinhard Arlt * data path. 87c2e49f70SReinhard Arlt */ 88c2e49f70SReinhard Arlt #undef CONFIG_DDR_32BIT 89c2e49f70SReinhard Arlt 90c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ 91c2e49f70SReinhard Arlt #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 92c2e49f70SReinhard Arlt #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 932fef4020SJoe Hershberger #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 942fef4020SJoe Hershberger | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 95c2e49f70SReinhard Arlt #define CONFIG_DDR_2T_TIMING 962fef4020SJoe Hershberger #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 972fef4020SJoe Hershberger | DDRCDR_ODT \ 982fef4020SJoe Hershberger | DDRCDR_Q_DRN) 992fef4020SJoe Hershberger /* 0x80080001 */ 100c2e49f70SReinhard Arlt 101c2e49f70SReinhard Arlt /* 102c2e49f70SReinhard Arlt * FLASH on the Local Bus 103c2e49f70SReinhard Arlt */ 104c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_CFI 105c2e49f70SReinhard Arlt #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 1061dee9be6SReinhard Arlt #ifdef VME_CADDY2 1071dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 1081dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 109c2e49f70SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1107d6a0982SJoe Hershberger BR_PS_16 | /* 16bit */ \ 1117d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 112c2e49f70SReinhard Arlt BR_V) /* valid */ 113c2e49f70SReinhard Arlt 1147d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 1157d6a0982SJoe Hershberger | OR_GPCM_XAM \ 1167d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 1177d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 1187d6a0982SJoe Hershberger | OR_GPCM_XACS \ 1197d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 1207d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 1217d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 1227d6a0982SJoe Hershberger | OR_GPCM_EAD) 1237d6a0982SJoe Hershberger /* 0xffc06ff7 */ 124c2e49f70SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1257d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) 1261dee9be6SReinhard Arlt #else 1271dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ 1281dee9be6SReinhard Arlt #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ 1291dee9be6SReinhard Arlt #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ 1307d6a0982SJoe Hershberger BR_PS_16 | /* 16bit */ \ 1317d6a0982SJoe Hershberger BR_MS_GPCM | /* MSEL = GPCM */ \ 1321dee9be6SReinhard Arlt BR_V) /* valid */ 1331dee9be6SReinhard Arlt 1347d6a0982SJoe Hershberger #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 1357d6a0982SJoe Hershberger | OR_GPCM_XAM \ 1367d6a0982SJoe Hershberger | OR_GPCM_CSNT \ 1377d6a0982SJoe Hershberger | OR_GPCM_ACS_DIV2 \ 1387d6a0982SJoe Hershberger | OR_GPCM_XACS \ 1397d6a0982SJoe Hershberger | OR_GPCM_SCY_15 \ 1407d6a0982SJoe Hershberger | OR_GPCM_TRLX_SET \ 1417d6a0982SJoe Hershberger | OR_GPCM_EHTR_SET \ 1427d6a0982SJoe Hershberger | OR_GPCM_EAD) 1437d6a0982SJoe Hershberger /* 0xf8006ff7 */ 1441dee9be6SReinhard Arlt #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 1457d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) 1461dee9be6SReinhard Arlt #endif 1471dee9be6SReinhard Arlt /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ 148c2e49f70SReinhard Arlt 1497d6a0982SJoe Hershberger #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 1507d6a0982SJoe Hershberger #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ 1517d6a0982SJoe Hershberger | BR_PS_32 \ 1527d6a0982SJoe Hershberger | BR_MS_GPCM \ 1537d6a0982SJoe Hershberger | BR_V) 1547d6a0982SJoe Hershberger /* 0xF0001801 */ 1557d6a0982SJoe Hershberger #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ 1567d6a0982SJoe Hershberger | OR_GPCM_SETA) 1577d6a0982SJoe Hershberger /* 0xfffc0208 */ 1587d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE 1597d6a0982SJoe Hershberger #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) 160c2e49f70SReinhard Arlt 161c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 162c2e49f70SReinhard Arlt #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 163c2e49f70SReinhard Arlt 164c2e49f70SReinhard Arlt #undef CONFIG_SYS_FLASH_CHECKSUM 165c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 166c2e49f70SReinhard Arlt #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 167c2e49f70SReinhard Arlt 16814d0a02aSWolfgang Denk #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 169c2e49f70SReinhard Arlt 170c2e49f70SReinhard Arlt #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 171c2e49f70SReinhard Arlt #define CONFIG_SYS_RAMBOOT 172c2e49f70SReinhard Arlt #else 173c2e49f70SReinhard Arlt #undef CONFIG_SYS_RAMBOOT 174c2e49f70SReinhard Arlt #endif 175c2e49f70SReinhard Arlt 176c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_LOCK 1 177c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 178553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 179c2e49f70SReinhard Arlt 180553f0982SWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 18125ddd1fbSWolfgang Denk GENERATED_GBL_DATA_SIZE) 182c2e49f70SReinhard Arlt #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 183c2e49f70SReinhard Arlt 184c2e49f70SReinhard Arlt #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 185c8a90646SKim Phillips #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ 186c2e49f70SReinhard Arlt 187c2e49f70SReinhard Arlt /* 188c2e49f70SReinhard Arlt * Local Bus LCRR and LBCR regs 1891dee9be6SReinhard Arlt * LCRR: no DLL bypass, Clock divider is 4 190c2e49f70SReinhard Arlt * External Local Bus rate is 191c2e49f70SReinhard Arlt * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV 192c2e49f70SReinhard Arlt */ 193c7190f02SKim Phillips #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 194c2e49f70SReinhard Arlt #define CONFIG_SYS_LBC_LBCR 0x00000000 195c2e49f70SReinhard Arlt 196c2e49f70SReinhard Arlt #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 197c2e49f70SReinhard Arlt 198c2e49f70SReinhard Arlt /* 199c2e49f70SReinhard Arlt * Serial Port 200c2e49f70SReinhard Arlt */ 201c2e49f70SReinhard Arlt #define CONFIG_CONS_INDEX 1 202c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550 203c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_SERIAL 204c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_REG_SIZE 1 205c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 206c2e49f70SReinhard Arlt 207c2e49f70SReinhard Arlt #define CONFIG_SYS_BAUDRATE_TABLE \ 208c2e49f70SReinhard Arlt {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 209c2e49f70SReinhard Arlt 210c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 211c2e49f70SReinhard Arlt #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 212c2e49f70SReinhard Arlt 213c2e49f70SReinhard Arlt #define CONFIG_CMDLINE_EDITING /* add command line history */ 214a059e90eSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 215c2e49f70SReinhard Arlt /* Use the HUSH parser */ 216c2e49f70SReinhard Arlt #define CONFIG_SYS_HUSH_PARSER 217c2e49f70SReinhard Arlt 218c2e49f70SReinhard Arlt /* pass open firmware flat tree */ 219c2e49f70SReinhard Arlt #define CONFIG_OF_LIBFDT 220c2e49f70SReinhard Arlt #define CONFIG_OF_BOARD_SETUP 221c2e49f70SReinhard Arlt #define CONFIG_OF_STDOUT_VIA_ALIAS 222c2e49f70SReinhard Arlt 223c2e49f70SReinhard Arlt /* I2C */ 224c2e49f70SReinhard Arlt #define CONFIG_I2C_MULTI_BUS 225c2e49f70SReinhard Arlt #define CONFIG_HARD_I2C /* I2C with hardware support*/ 226c2e49f70SReinhard Arlt #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 227c2e49f70SReinhard Arlt #define CONFIG_FSL_I2C 228c2e49f70SReinhard Arlt #define CONFIG_I2C_CMD_TREE 229c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 230c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_SLAVE 0x7F 231c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ 232c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C1_OFFSET 0x3000 233c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C2_OFFSET 0x3100 234c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C1_OFFSET 235efaf6f1bSPaul Gortmaker /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 236c2e49f70SReinhard Arlt 237c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 238c2e49f70SReinhard Arlt 239c2e49f70SReinhard Arlt /* TSEC */ 240c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1_OFFSET 0x24000 241c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 242c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2_OFFSET 0x25000 243c2e49f70SReinhard Arlt #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 244c2e49f70SReinhard Arlt 245c2e49f70SReinhard Arlt /* 246c2e49f70SReinhard Arlt * General PCI 247c2e49f70SReinhard Arlt * Addresses are mapped 1-1. 248c2e49f70SReinhard Arlt */ 249c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 250c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 251c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 252c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 253c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 254c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 255c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 256c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 257c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 258c2e49f70SReinhard Arlt 259c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 260c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 261c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 262c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 263c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 264c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 265c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 266c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 267c2e49f70SReinhard Arlt #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 268c2e49f70SReinhard Arlt 269c2e49f70SReinhard Arlt #if defined(CONFIG_PCI) 270c2e49f70SReinhard Arlt 271c2e49f70SReinhard Arlt #define PCI_64BIT 272c2e49f70SReinhard Arlt #define PCI_ONE_PCI1 273c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 274c2e49f70SReinhard Arlt #undef PCI_ALL_PCI1 275c2e49f70SReinhard Arlt #undef PCI_TWO_PCI1 276c2e49f70SReinhard Arlt #undef PCI_ONE_PCI1 277c2e49f70SReinhard Arlt #endif 278c2e49f70SReinhard Arlt 2791dee9be6SReinhard Arlt #ifndef VME_CADDY2 2801dee9be6SReinhard Arlt #endif 2811dee9be6SReinhard Arlt #define CONFIG_PCI_PNP /* do pci plug-and-play */ 282c2e49f70SReinhard Arlt 283c2e49f70SReinhard Arlt #undef CONFIG_EEPRO100 284c2e49f70SReinhard Arlt #undef CONFIG_TULIP 285c2e49f70SReinhard Arlt 286c2e49f70SReinhard Arlt #if !defined(CONFIG_PCI_PNP) 287c2e49f70SReinhard Arlt #define PCI_ENET0_IOADDR 0xFIXME 288c2e49f70SReinhard Arlt #define PCI_ENET0_MEMADDR 0xFIXME 289c2e49f70SReinhard Arlt #define PCI_IDSEL_NUMBER 0xFIXME 290c2e49f70SReinhard Arlt #endif 291c2e49f70SReinhard Arlt 2921dee9be6SReinhard Arlt #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 2931dee9be6SReinhard Arlt #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 2941dee9be6SReinhard Arlt 295c2e49f70SReinhard Arlt #endif /* CONFIG_PCI */ 296c2e49f70SReinhard Arlt 297c2e49f70SReinhard Arlt /* 298c2e49f70SReinhard Arlt * TSEC configuration 299c2e49f70SReinhard Arlt */ 3001dee9be6SReinhard Arlt #ifdef VME_CADDY2 3011dee9be6SReinhard Arlt #define CONFIG_E1000 3021dee9be6SReinhard Arlt #else 303c2e49f70SReinhard Arlt #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 3041dee9be6SReinhard Arlt #endif 305c2e49f70SReinhard Arlt 306c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 307c2e49f70SReinhard Arlt 308c2e49f70SReinhard Arlt #define CONFIG_GMII /* MII PHY management */ 309c2e49f70SReinhard Arlt #define CONFIG_TSEC1 310c2e49f70SReinhard Arlt #define CONFIG_TSEC1_NAME "TSEC0" 311c2e49f70SReinhard Arlt #define CONFIG_TSEC2 312c2e49f70SReinhard Arlt #define CONFIG_TSEC2_NAME "TSEC1" 313c2e49f70SReinhard Arlt #define CONFIG_PHY_M88E1111 314c2e49f70SReinhard Arlt #define TSEC1_PHY_ADDR 0x08 315c2e49f70SReinhard Arlt #define TSEC2_PHY_ADDR 0x10 316c2e49f70SReinhard Arlt #define TSEC1_PHYIDX 0 317c2e49f70SReinhard Arlt #define TSEC2_PHYIDX 0 318c2e49f70SReinhard Arlt #define TSEC1_FLAGS TSEC_GIGABIT 319c2e49f70SReinhard Arlt #define TSEC2_FLAGS TSEC_GIGABIT 320c2e49f70SReinhard Arlt 321c2e49f70SReinhard Arlt /* Options are: TSEC[0-1] */ 322c2e49f70SReinhard Arlt #define CONFIG_ETHPRIME "TSEC0" 323c2e49f70SReinhard Arlt 324c2e49f70SReinhard Arlt #endif /* CONFIG_TSEC_ENET */ 325c2e49f70SReinhard Arlt 326c2e49f70SReinhard Arlt /* 327c2e49f70SReinhard Arlt * Environment 328c2e49f70SReinhard Arlt */ 329c2e49f70SReinhard Arlt #ifndef CONFIG_SYS_RAMBOOT 330c2e49f70SReinhard Arlt #define CONFIG_ENV_IS_IN_FLASH 331c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) 332c2e49f70SReinhard Arlt #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 333c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 334c2e49f70SReinhard Arlt 335c2e49f70SReinhard Arlt /* Address and size of Redundant Environment Sector */ 336c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 337c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 338c2e49f70SReinhard Arlt 339c2e49f70SReinhard Arlt #else 340c2e49f70SReinhard Arlt #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ 341c2e49f70SReinhard Arlt #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 342c2e49f70SReinhard Arlt #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 343c2e49f70SReinhard Arlt #define CONFIG_ENV_SIZE 0x2000 344c2e49f70SReinhard Arlt #endif 345c2e49f70SReinhard Arlt 346c2e49f70SReinhard Arlt #define CONFIG_LOADS_ECHO /* echo on for serial download */ 347c2e49f70SReinhard Arlt #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 348c2e49f70SReinhard Arlt 349c2e49f70SReinhard Arlt /* 350c2e49f70SReinhard Arlt * BOOTP options 351c2e49f70SReinhard Arlt */ 352c2e49f70SReinhard Arlt #define CONFIG_BOOTP_BOOTFILESIZE 353c2e49f70SReinhard Arlt #define CONFIG_BOOTP_BOOTPATH 354c2e49f70SReinhard Arlt #define CONFIG_BOOTP_GATEWAY 355c2e49f70SReinhard Arlt #define CONFIG_BOOTP_HOSTNAME 356c2e49f70SReinhard Arlt 357c2e49f70SReinhard Arlt /* 358c2e49f70SReinhard Arlt * Command line configuration. 359c2e49f70SReinhard Arlt */ 360c2e49f70SReinhard Arlt #include <config_cmd_default.h> 361c2e49f70SReinhard Arlt 362c2e49f70SReinhard Arlt #define CONFIG_CMD_I2C 363c2e49f70SReinhard Arlt #define CONFIG_CMD_MII 364c2e49f70SReinhard Arlt #define CONFIG_CMD_PING 365c2e49f70SReinhard Arlt #define CONFIG_CMD_DATE 366c2e49f70SReinhard Arlt #define CONFIG_SYS_RTC_BUS_NUM 0x01 367c2e49f70SReinhard Arlt #define CONFIG_SYS_I2C_RTC_ADDR 0x32 368c2e49f70SReinhard Arlt #define CONFIG_RTC_RX8025 369c2e49f70SReinhard Arlt #define CONFIG_CMD_TSI148 370c2e49f70SReinhard Arlt 371c2e49f70SReinhard Arlt #if defined(CONFIG_PCI) 372c2e49f70SReinhard Arlt #define CONFIG_CMD_PCI 373c2e49f70SReinhard Arlt #endif 374c2e49f70SReinhard Arlt 375c2e49f70SReinhard Arlt #if defined(CONFIG_SYS_RAMBOOT) 376c2e49f70SReinhard Arlt #undef CONFIG_CMD_ENV 377c2e49f70SReinhard Arlt #undef CONFIG_CMD_LOADS 378c2e49f70SReinhard Arlt #endif 379c2e49f70SReinhard Arlt 380c2e49f70SReinhard Arlt #define CONFIG_CMD_ELF 381c2e49f70SReinhard Arlt /* Pass Ethernet MAC to VxWorks */ 382c2e49f70SReinhard Arlt #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 383c2e49f70SReinhard Arlt 384c2e49f70SReinhard Arlt #undef CONFIG_WATCHDOG /* watchdog disabled */ 385c2e49f70SReinhard Arlt 386c2e49f70SReinhard Arlt /* 387c2e49f70SReinhard Arlt * Miscellaneous configurable options 388c2e49f70SReinhard Arlt */ 389c2e49f70SReinhard Arlt #define CONFIG_SYS_LONGHELP /* undef to save memory */ 390c2e49f70SReinhard Arlt #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 391c2e49f70SReinhard Arlt #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 392c2e49f70SReinhard Arlt 393c2e49f70SReinhard Arlt #if defined(CONFIG_CMD_KGDB) 394c2e49f70SReinhard Arlt #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 395c2e49f70SReinhard Arlt #else 396c2e49f70SReinhard Arlt #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 397c2e49f70SReinhard Arlt #endif 398c2e49f70SReinhard Arlt 399c2e49f70SReinhard Arlt #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 400c2e49f70SReinhard Arlt #define CONFIG_SYS_MAXARGS 16 /* max num of command args */ 401c2e49f70SReinhard Arlt #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */ 402c2e49f70SReinhard Arlt #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 403c2e49f70SReinhard Arlt 404c2e49f70SReinhard Arlt /* 405c2e49f70SReinhard Arlt * For booting Linux, the board info and command line data 4069f530d59SIra W. Snyder * have to be in the first 256 MB of memory, since this is 407c2e49f70SReinhard Arlt * the maximum mapped by the Linux kernel during initialization. 408c2e49f70SReinhard Arlt */ 4099f530d59SIra W. Snyder #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 410c2e49f70SReinhard Arlt 411c2e49f70SReinhard Arlt #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 412c2e49f70SReinhard Arlt 413c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_LOW (\ 414c2e49f70SReinhard Arlt HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ 415c2e49f70SReinhard Arlt HRCWL_DDR_TO_SCB_CLK_1X1 |\ 416c2e49f70SReinhard Arlt HRCWL_CSB_TO_CLKIN |\ 417c2e49f70SReinhard Arlt HRCWL_VCO_1X2 |\ 418c2e49f70SReinhard Arlt HRCWL_CORE_TO_CSB_2X1) 419c2e49f70SReinhard Arlt 420c2e49f70SReinhard Arlt #if defined(PCI_64BIT) 421c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 422c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 423c2e49f70SReinhard Arlt HRCWH_64_BIT_PCI |\ 424c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 425c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_DISABLE |\ 426c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 427c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 428c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 429c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 430c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 431c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 432c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 433c2e49f70SReinhard Arlt #else 434c2e49f70SReinhard Arlt #define CONFIG_SYS_HRCW_HIGH (\ 435c2e49f70SReinhard Arlt HRCWH_PCI_HOST |\ 436c2e49f70SReinhard Arlt HRCWH_32_BIT_PCI |\ 437c2e49f70SReinhard Arlt HRCWH_PCI1_ARBITER_ENABLE |\ 438c2e49f70SReinhard Arlt HRCWH_PCI2_ARBITER_ENABLE |\ 439c2e49f70SReinhard Arlt HRCWH_CORE_ENABLE |\ 440c2e49f70SReinhard Arlt HRCWH_FROM_0X00000100 |\ 441c2e49f70SReinhard Arlt HRCWH_BOOTSEQ_DISABLE |\ 442c2e49f70SReinhard Arlt HRCWH_SW_WATCHDOG_DISABLE |\ 443c2e49f70SReinhard Arlt HRCWH_ROM_LOC_LOCAL_16BIT |\ 444c2e49f70SReinhard Arlt HRCWH_TSEC1M_IN_GMII |\ 445c2e49f70SReinhard Arlt HRCWH_TSEC2M_IN_GMII) 446c2e49f70SReinhard Arlt #endif 447c2e49f70SReinhard Arlt 448c2e49f70SReinhard Arlt /* System IO Config */ 449c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRH 0 450c2e49f70SReinhard Arlt #define CONFIG_SYS_SICRL SICRL_LDP_A 451c2e49f70SReinhard Arlt 452c2e49f70SReinhard Arlt #define CONFIG_SYS_HID0_INIT 0x000000000 4531a2e203bSKim Phillips #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 4541a2e203bSKim Phillips HID0_ENABLE_INSTRUCTION_CACHE) 455c2e49f70SReinhard Arlt 456c2e49f70SReinhard Arlt #define CONFIG_SYS_HID2 HID2_HBE 457c2e49f70SReinhard Arlt 458c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_PRELIM 459c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DIR 0x00100000 460c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO1_DAT 0x00100000 461c2e49f70SReinhard Arlt 462c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_PRELIM 463c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DIR 0x78900000 464c2e49f70SReinhard Arlt #define CONFIG_SYS_GPIO2_DAT 0x70100000 465c2e49f70SReinhard Arlt 466c2e49f70SReinhard Arlt #define CONFIG_HIGH_BATS /* High BATs supported */ 467c2e49f70SReinhard Arlt 468c2e49f70SReinhard Arlt /* DDR @ 0x00000000 */ 46972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ 470c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 471c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 472c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 473c2e49f70SReinhard Arlt 474c2e49f70SReinhard Arlt /* PCI @ 0x80000000 */ 475c2e49f70SReinhard Arlt #ifdef CONFIG_PCI 476842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 47772cd4087SJoe Hershberger #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ 478c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 479c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 480c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 48172cd4087SJoe Hershberger #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ 482c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 483c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 484c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 485c2e49f70SReinhard Arlt #else 486c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1L (0) 487c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT1U (0) 488c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2L (0) 489c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT2U (0) 490c2e49f70SReinhard Arlt #endif 491c2e49f70SReinhard Arlt 492c2e49f70SReinhard Arlt #ifdef CONFIG_MPC83XX_PCI2 49372cd4087SJoe Hershberger #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ 494c2e49f70SReinhard Arlt BATL_MEMCOHERENCE) 495c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ 496c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 49772cd4087SJoe Hershberger #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ 498c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 499c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ 500c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 501c2e49f70SReinhard Arlt #else 502c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3L (0) 503c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT3U (0) 504c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4L (0) 505c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT4U (0) 506c2e49f70SReinhard Arlt #endif 507c2e49f70SReinhard Arlt 508c2e49f70SReinhard Arlt /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ 50972cd4087SJoe Hershberger #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ 510c2e49f70SReinhard Arlt BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 511c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ 512c2e49f70SReinhard Arlt BATU_VS | BATU_VP) 513c2e49f70SReinhard Arlt 51472cd4087SJoe Hershberger #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) 515c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 516c2e49f70SReinhard Arlt 517c2e49f70SReinhard Arlt #if (CONFIG_SYS_DDR_SIZE == 512) 518c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 51972cd4087SJoe Hershberger BATL_PP_RW | BATL_MEMCOHERENCE) 520c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ 521c2e49f70SReinhard Arlt BATU_BL_256M | BATU_VS | BATU_VP) 522c2e49f70SReinhard Arlt #else 523c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7L (0) 524c2e49f70SReinhard Arlt #define CONFIG_SYS_IBAT7U (0) 525c2e49f70SReinhard Arlt #endif 526c2e49f70SReinhard Arlt 527c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 528c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 529c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 530c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 531c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 532c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 533c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 534c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 535c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 536c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 537c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 538c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 539c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 540c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 541c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 542c2e49f70SReinhard Arlt #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 543c2e49f70SReinhard Arlt 544c2e49f70SReinhard Arlt #if defined(CONFIG_CMD_KGDB) 545c2e49f70SReinhard Arlt #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 546c2e49f70SReinhard Arlt #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 547c2e49f70SReinhard Arlt #endif 548c2e49f70SReinhard Arlt 549c2e49f70SReinhard Arlt /* 550c2e49f70SReinhard Arlt * Environment Configuration 551c2e49f70SReinhard Arlt */ 552c2e49f70SReinhard Arlt #define CONFIG_ENV_OVERWRITE 553c2e49f70SReinhard Arlt 554c2e49f70SReinhard Arlt #if defined(CONFIG_TSEC_ENET) 555c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH0 556c2e49f70SReinhard Arlt #define CONFIG_HAS_ETH1 557c2e49f70SReinhard Arlt #endif 558c2e49f70SReinhard Arlt 559c2e49f70SReinhard Arlt #define CONFIG_HOSTNAME VME8349 5608b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/tftpboot/rootfs" 561b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 562c2e49f70SReinhard Arlt 56379f516bcSKim Phillips #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 564c2e49f70SReinhard Arlt 565c2e49f70SReinhard Arlt #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 566c2e49f70SReinhard Arlt #undef CONFIG_BOOTARGS /* boot command will set bootargs */ 567c2e49f70SReinhard Arlt 5681dee9be6SReinhard Arlt #define CONFIG_BAUDRATE 9600 569c2e49f70SReinhard Arlt 570c2e49f70SReinhard Arlt #define CONFIG_EXTRA_ENV_SETTINGS \ 571c2e49f70SReinhard Arlt "netdev=eth0\0" \ 572c2e49f70SReinhard Arlt "hostname=vme8349\0" \ 573c2e49f70SReinhard Arlt "nfsargs=setenv bootargs root=/dev/nfs rw " \ 574c2e49f70SReinhard Arlt "nfsroot=${serverip}:${rootpath}\0" \ 575c2e49f70SReinhard Arlt "ramargs=setenv bootargs root=/dev/ram rw\0" \ 576c2e49f70SReinhard Arlt "addip=setenv bootargs ${bootargs} " \ 577c2e49f70SReinhard Arlt "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 578c2e49f70SReinhard Arlt ":${hostname}:${netdev}:off panic=1\0" \ 579c2e49f70SReinhard Arlt "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 580c2e49f70SReinhard Arlt "flash_nfs=run nfsargs addip addtty;" \ 581c2e49f70SReinhard Arlt "bootm ${kernel_addr}\0" \ 582c2e49f70SReinhard Arlt "flash_self=run ramargs addip addtty;" \ 583c2e49f70SReinhard Arlt "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 584c2e49f70SReinhard Arlt "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 585c2e49f70SReinhard Arlt "bootm\0" \ 586c2e49f70SReinhard Arlt "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 587c2e49f70SReinhard Arlt "update=protect off fff00000 fff3ffff; " \ 588c2e49f70SReinhard Arlt "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 589c2e49f70SReinhard Arlt "upd=run load update\0" \ 59079f516bcSKim Phillips "fdtaddr=780000\0" \ 591c2e49f70SReinhard Arlt "fdtfile=vme8349.dtb\0" \ 592c2e49f70SReinhard Arlt "" 593c2e49f70SReinhard Arlt 594c2e49f70SReinhard Arlt #define CONFIG_NFSBOOTCOMMAND \ 595c2e49f70SReinhard Arlt "setenv bootargs root=/dev/nfs rw " \ 596c2e49f70SReinhard Arlt "nfsroot=$serverip:$rootpath " \ 597c7357a2bSJoe Hershberger "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 598c7357a2bSJoe Hershberger "$netdev:off " \ 599c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 600c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 601c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 602c2e49f70SReinhard Arlt "bootm $loadaddr - $fdtaddr" 603c2e49f70SReinhard Arlt 604c2e49f70SReinhard Arlt #define CONFIG_RAMBOOTCOMMAND \ 605c2e49f70SReinhard Arlt "setenv bootargs root=/dev/ram rw " \ 606c2e49f70SReinhard Arlt "console=$consoledev,$baudrate $othbootargs;" \ 607c2e49f70SReinhard Arlt "tftp $ramdiskaddr $ramdiskfile;" \ 608c2e49f70SReinhard Arlt "tftp $loadaddr $bootfile;" \ 609c2e49f70SReinhard Arlt "tftp $fdtaddr $fdtfile;" \ 610c2e49f70SReinhard Arlt "bootm $loadaddr $ramdiskaddr $fdtaddr" 611c2e49f70SReinhard Arlt 612c2e49f70SReinhard Arlt #define CONFIG_BOOTCOMMAND "run flash_self" 613c2e49f70SReinhard Arlt 6141dee9be6SReinhard Arlt #ifndef __ASSEMBLY__ 6151dee9be6SReinhard Arlt int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 6161dee9be6SReinhard Arlt unsigned char *buffer, int len); 6171dee9be6SReinhard Arlt #endif 6181dee9be6SReinhard Arlt 619c2e49f70SReinhard Arlt #endif /* __CONFIG_H */ 620