1 /*
2  * (C) Copyright 2011 ARM Limited
3  * (C) Copyright 2010 Linaro
4  * Matt Waddel, <matt.waddel@linaro.org>
5  *
6  * Configuration for Versatile Express. Parts were derived from other ARM
7  *   configurations.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #ifndef __VEXPRESS_COMMON_H
13 #define __VEXPRESS_COMMON_H
14 
15 /*
16  * Definitions copied from linux kernel:
17  * arch/arm/mach-vexpress/include/mach/motherboard.h
18  */
19 #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
20 /* CS register bases for the original memory map. */
21 #define V2M_PA_CS0		0x40000000
22 #define V2M_PA_CS1		0x44000000
23 #define V2M_PA_CS2		0x48000000
24 #define V2M_PA_CS3		0x4c000000
25 #define V2M_PA_CS7		0x10000000
26 
27 #define V2M_PERIPH_OFFSET(x)	(x << 12)
28 #define V2M_SYSREGS		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
29 #define V2M_SYSCTL		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
30 #define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
31 
32 #define V2M_BASE		0x60000000
33 #define CONFIG_SYS_TEXT_BASE	0x60800000
34 #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
35 /* CS register bases for the extended memory map. */
36 #define V2M_PA_CS0		0x08000000
37 #define V2M_PA_CS1		0x0c000000
38 #define V2M_PA_CS2		0x14000000
39 #define V2M_PA_CS3		0x18000000
40 #define V2M_PA_CS7		0x1c000000
41 
42 #define V2M_PERIPH_OFFSET(x)	(x << 16)
43 #define V2M_SYSREGS		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
44 #define V2M_SYSCTL		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
45 #define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
46 
47 #define V2M_BASE		0x80000000
48 #define CONFIG_SYS_TEXT_BASE	0x80800000
49 #endif
50 
51 /*
52  * Physical addresses, offset from V2M_PA_CS0-3
53  */
54 #define V2M_NOR0		(V2M_PA_CS0)
55 #define V2M_NOR1		(V2M_PA_CS1)
56 #define V2M_SRAM		(V2M_PA_CS2)
57 #define V2M_VIDEO_SRAM		(V2M_PA_CS3 + 0x00000000)
58 #define V2M_LAN9118		(V2M_PA_CS3 + 0x02000000)
59 #define V2M_ISP1761		(V2M_PA_CS3 + 0x03000000)
60 
61 /* Common peripherals relative to CS7. */
62 #define V2M_AACI		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
63 #define V2M_MMCI		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
64 #define V2M_KMI0		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
65 #define V2M_KMI1		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
66 
67 #define V2M_UART0		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
68 #define V2M_UART1		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
69 #define V2M_UART2		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
70 #define V2M_UART3		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
71 
72 #define V2M_WDT			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
73 
74 #define V2M_TIMER01		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
75 #define V2M_TIMER23		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
76 
77 #define V2M_SERIAL_BUS_DVI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
78 #define V2M_RTC			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
79 
80 #define V2M_CF			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
81 
82 #define V2M_CLCD		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
83 #define V2M_SIZE_CS7		V2M_PERIPH_OFFSET(32)
84 
85 /* System register offsets. */
86 #define V2M_SYS_CFGDATA		(V2M_SYSREGS + 0x0a0)
87 #define V2M_SYS_CFGCTRL		(V2M_SYSREGS + 0x0a4)
88 #define V2M_SYS_CFGSTAT		(V2M_SYSREGS + 0x0a8)
89 
90 /*
91  * Configuration
92  */
93 #define SYS_CFG_START		(1 << 31)
94 #define SYS_CFG_WRITE		(1 << 30)
95 #define SYS_CFG_OSC		(1 << 20)
96 #define SYS_CFG_VOLT		(2 << 20)
97 #define SYS_CFG_AMP		(3 << 20)
98 #define SYS_CFG_TEMP		(4 << 20)
99 #define SYS_CFG_RESET		(5 << 20)
100 #define SYS_CFG_SCC		(6 << 20)
101 #define SYS_CFG_MUXFPGA		(7 << 20)
102 #define SYS_CFG_SHUTDOWN	(8 << 20)
103 #define SYS_CFG_REBOOT		(9 << 20)
104 #define SYS_CFG_DVIMODE		(11 << 20)
105 #define SYS_CFG_POWER		(12 << 20)
106 #define SYS_CFG_SITE_MB		(0 << 16)
107 #define SYS_CFG_SITE_DB1	(1 << 16)
108 #define SYS_CFG_SITE_DB2	(2 << 16)
109 #define SYS_CFG_STACK(n)	((n) << 12)
110 
111 #define SYS_CFG_ERR		(1 << 1)
112 #define SYS_CFG_COMPLETE	(1 << 0)
113 
114 /* Board info register */
115 #define SYS_ID				V2M_SYSREGS
116 #define CONFIG_REVISION_TAG		1
117 
118 #define CONFIG_SYS_MEMTEST_START	V2M_BASE
119 #define CONFIG_SYS_MEMTEST_END		0x20000000
120 
121 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
122 #define CONFIG_SETUP_MEMORY_TAGS	1
123 #define CONFIG_SYS_L2CACHE_OFF		1
124 #define CONFIG_INITRD_TAG		1
125 
126 /* Size of malloc() pool */
127 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
128 
129 #define SCTL_BASE			V2M_SYSCTL
130 #define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
131 
132 #define CONFIG_SYS_TIMER_RATE		1000000
133 #define CONFIG_SYS_TIMER_COUNTER	(V2M_TIMER01 + 0x4)
134 #define CONFIG_SYS_TIMER_COUNTS_DOWN
135 
136 /* SMSC9115 Ethernet from SMSC9118 family */
137 #define CONFIG_SMC911X			1
138 #define CONFIG_SMC911X_32_BIT		1
139 #define CONFIG_SMC911X_BASE		V2M_LAN9118
140 
141 /* PL011 Serial Configuration */
142 #define CONFIG_PL011_SERIAL
143 #define CONFIG_PL011_CLOCK		24000000
144 #define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
145 					 (void *)CONFIG_SYS_SERIAL1}
146 #define CONFIG_CONS_INDEX		0
147 
148 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
149 #define CONFIG_SYS_SERIAL0		V2M_UART0
150 #define CONFIG_SYS_SERIAL1		V2M_UART1
151 
152 #define CONFIG_ARM_PL180_MMCI
153 #define CONFIG_ARM_PL180_MMCI_BASE	V2M_MMCI
154 #define CONFIG_SYS_MMC_MAX_BLK_COUNT	127
155 #define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
156 
157 /* BOOTP options */
158 #define CONFIG_BOOTP_BOOTFILESIZE
159 #define CONFIG_BOOTP_BOOTPATH
160 #define CONFIG_BOOTP_GATEWAY
161 #define CONFIG_BOOTP_HOSTNAME
162 
163 /* Miscellaneous configurable options */
164 #define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x8000)
165 #define LINUX_BOOT_PARAM_ADDR		(V2M_BASE + 0x2000)
166 
167 /* Physical Memory Map */
168 #define CONFIG_NR_DRAM_BANKS		2
169 #define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
170 #define PHYS_SDRAM_2			(((unsigned int)V2M_BASE) + \
171 					((unsigned int)0x20000000))
172 #define PHYS_SDRAM_1_SIZE		0x20000000	/* 512 MB */
173 #define PHYS_SDRAM_2_SIZE		0x20000000	/* 512 MB */
174 
175 /* additions for new relocation code */
176 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
177 #define CONFIG_SYS_INIT_RAM_SIZE		0x1000
178 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
179 					 CONFIG_SYS_INIT_RAM_SIZE - \
180 					 GENERATED_GBL_DATA_SIZE)
181 #define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
182 
183 #include <config_distro_defaults.h>
184 
185 /* Basic environment settings */
186 #define CONFIG_BOOTCOMMAND \
187 	"run distro_bootcmd; " \
188 	"run bootflash; "
189 
190 #define BOOT_TARGET_DEVICES(func) \
191         func(MMC, mmc, 1) \
192         func(MMC, mmc, 0) \
193         func(PXE, pxe, na) \
194         func(DHCP, dhcp, na)
195 #include <config_distro_bootcmd.h>
196 
197 #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
198 #define CONFIG_PLATFORM_ENV_SETTINGS \
199 		"loadaddr=0x80008000\0" \
200 		"ramdisk_addr_r=0x61000000\0" \
201 		"kernel_addr=0x44100000\0" \
202 		"ramdisk_addr=0x44800000\0" \
203 		"maxramdisk=0x1800000\0" \
204 		"pxefile_addr_r=0x88000000\0" \
205 		"scriptaddr=0x88000000\0" \
206 		"kernel_addr_r=0x80008000\0"
207 #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
208 #define CONFIG_PLATFORM_ENV_SETTINGS \
209 		"loadaddr=0xa0008000\0" \
210 		"ramdisk_addr_r=0x81000000\0" \
211 		"kernel_addr=0x0c100000\0" \
212 		"ramdisk_addr=0x0c800000\0" \
213 		"maxramdisk=0x1800000\0" \
214 		"pxefile_addr_r=0xa8000000\0" \
215 		"scriptaddr=0xa8000000\0" \
216 		"kernel_addr_r=0xa0008000\0"
217 #endif
218 #define CONFIG_EXTRA_ENV_SETTINGS \
219 		CONFIG_PLATFORM_ENV_SETTINGS \
220                 BOOTENV \
221 		"console=ttyAMA0,38400n8\0" \
222 		"dram=1024M\0" \
223 		"root=/dev/sda1 rw\0" \
224 		"mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
225 			"24M@0x2000000(initrd)\0" \
226 		"flashargs=setenv bootargs root=${root} console=${console} " \
227 			"mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
228 			"devtmpfs.mount=0  vmalloc=256M\0" \
229 		"bootflash=run flashargs; " \
230 			"cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
231 			"bootm ${kernel_addr} ${ramdisk_addr_r}\0"
232 
233 /* FLASH and environment organization */
234 #define PHYS_FLASH_SIZE			0x04000000	/* 64MB */
235 #define CONFIG_SYS_FLASH_CFI		1
236 #define CONFIG_FLASH_CFI_DRIVER		1
237 #define CONFIG_SYS_FLASH_SIZE		0x04000000
238 #define CONFIG_SYS_MAX_FLASH_BANKS	2
239 #define CONFIG_SYS_FLASH_BASE0		V2M_NOR0
240 #define CONFIG_SYS_FLASH_BASE1		V2M_NOR1
241 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE0
242 
243 /* Timeout values in ticks */
244 #define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
245 #define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */
246 
247 /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
248 #define CONFIG_SYS_MAX_FLASH_SECT	259		/* Max sectors */
249 #define FLASH_MAX_SECTOR_SIZE		0x00040000	/* 256 KB sectors */
250 
251 /* Room required on the stack for the environment data */
252 #define CONFIG_ENV_SIZE			FLASH_MAX_SECTOR_SIZE
253 
254 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
255 
256 /*
257  * Amount of flash used for environment:
258  * We don't know which end has the small erase blocks so we use the penultimate
259  * sector location for the environment
260  */
261 #define CONFIG_ENV_SECT_SIZE		FLASH_MAX_SECTOR_SIZE
262 #define CONFIG_ENV_OVERWRITE		1
263 
264 /* Store environment at top of flash */
265 #define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - \
266 					(2 * CONFIG_ENV_SECT_SIZE))
267 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE1 + \
268 					 CONFIG_ENV_OFFSET)
269 #define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
270 #define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
271 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE0, \
272 					  CONFIG_SYS_FLASH_BASE1 }
273 
274 /* Monitor Command Prompt */
275 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
276 #define CONFIG_SYS_LONGHELP
277 
278 #endif /* VEXPRESS_COMMON_H */
279