19b58a3f6SRyan Harkin /*
2*cd4f46e1SRyan Harkin  * (C) Copyright 2011 ARM Limited
39b58a3f6SRyan Harkin  * (C) Copyright 2010 Linaro
49b58a3f6SRyan Harkin  * Matt Waddel, <matt.waddel@linaro.org>
59b58a3f6SRyan Harkin  *
69b58a3f6SRyan Harkin  * Configuration for Versatile Express. Parts were derived from other ARM
79b58a3f6SRyan Harkin  *   configurations.
89b58a3f6SRyan Harkin  *
99b58a3f6SRyan Harkin  * See file CREDITS for list of people who contributed to this
109b58a3f6SRyan Harkin  * project.
119b58a3f6SRyan Harkin  *
129b58a3f6SRyan Harkin  * This program is free software; you can redistribute it and/or
139b58a3f6SRyan Harkin  * modify it under the terms of the GNU General Public License as
149b58a3f6SRyan Harkin  * published by the Free Software Foundation; either version 2 of
159b58a3f6SRyan Harkin  * the License, or (at your option) any later version.
169b58a3f6SRyan Harkin  *
179b58a3f6SRyan Harkin  * This program is distributed in the hope that it will be useful,
189b58a3f6SRyan Harkin  * but WITHOUT ANY WARRANTY; without even the implied warranty of
199b58a3f6SRyan Harkin  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
209b58a3f6SRyan Harkin  * GNU General Public License for more details.
219b58a3f6SRyan Harkin  *
229b58a3f6SRyan Harkin  * You should have received a copy of the GNU General Public License
239b58a3f6SRyan Harkin  * along with this program; if not, write to the Free Software
249b58a3f6SRyan Harkin  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
259b58a3f6SRyan Harkin  * MA 02111-1307 USA
269b58a3f6SRyan Harkin  */
279b58a3f6SRyan Harkin 
28*cd4f46e1SRyan Harkin #ifndef __VEXPRESS_COMMON_H
29*cd4f46e1SRyan Harkin #define __VEXPRESS_COMMON_H
30*cd4f46e1SRyan Harkin 
31*cd4f46e1SRyan Harkin /*
32*cd4f46e1SRyan Harkin  * Definitions copied from linux kernel:
33*cd4f46e1SRyan Harkin  * arch/arm/mach-vexpress/include/mach/motherboard.h
34*cd4f46e1SRyan Harkin  */
35*cd4f46e1SRyan Harkin #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
36*cd4f46e1SRyan Harkin /* CS register bases for the original memory map. */
37*cd4f46e1SRyan Harkin #define V2M_PA_CS0		0x40000000
38*cd4f46e1SRyan Harkin #define V2M_PA_CS1		0x44000000
39*cd4f46e1SRyan Harkin #define V2M_PA_CS2		0x48000000
40*cd4f46e1SRyan Harkin #define V2M_PA_CS3		0x4c000000
41*cd4f46e1SRyan Harkin #define V2M_PA_CS7		0x10000000
42*cd4f46e1SRyan Harkin 
43*cd4f46e1SRyan Harkin #define V2M_PERIPH_OFFSET(x)	(x << 12)
44*cd4f46e1SRyan Harkin #define V2M_SYSREGS		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
45*cd4f46e1SRyan Harkin #define V2M_SYSCTL		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
46*cd4f46e1SRyan Harkin #define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
47*cd4f46e1SRyan Harkin 
48*cd4f46e1SRyan Harkin #define V2M_BASE		0x60000000
49*cd4f46e1SRyan Harkin #define CONFIG_SYS_TEXT_BASE	0x60800000
50*cd4f46e1SRyan Harkin #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
51*cd4f46e1SRyan Harkin /* CS register bases for the extended memory map. */
52*cd4f46e1SRyan Harkin #define V2M_PA_CS0		0x08000000
53*cd4f46e1SRyan Harkin #define V2M_PA_CS1		0x0c000000
54*cd4f46e1SRyan Harkin #define V2M_PA_CS2		0x14000000
55*cd4f46e1SRyan Harkin #define V2M_PA_CS3		0x18000000
56*cd4f46e1SRyan Harkin #define V2M_PA_CS7		0x1c000000
57*cd4f46e1SRyan Harkin 
58*cd4f46e1SRyan Harkin #define V2M_PERIPH_OFFSET(x)	(x << 16)
59*cd4f46e1SRyan Harkin #define V2M_SYSREGS		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
60*cd4f46e1SRyan Harkin #define V2M_SYSCTL		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
61*cd4f46e1SRyan Harkin #define V2M_SERIAL_BUS_PCI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
62*cd4f46e1SRyan Harkin 
63*cd4f46e1SRyan Harkin #define V2M_BASE		0x80000000
64*cd4f46e1SRyan Harkin #define CONFIG_SYS_TEXT_BASE	0x80800000
65*cd4f46e1SRyan Harkin #endif
66*cd4f46e1SRyan Harkin 
67*cd4f46e1SRyan Harkin /*
68*cd4f46e1SRyan Harkin  * Physical addresses, offset from V2M_PA_CS0-3
69*cd4f46e1SRyan Harkin  */
70*cd4f46e1SRyan Harkin #define V2M_NOR0		(V2M_PA_CS0)
71*cd4f46e1SRyan Harkin #define V2M_NOR1		(V2M_PA_CS1)
72*cd4f46e1SRyan Harkin #define V2M_SRAM		(V2M_PA_CS2)
73*cd4f46e1SRyan Harkin #define V2M_VIDEO_SRAM		(V2M_PA_CS3 + 0x00000000)
74*cd4f46e1SRyan Harkin #define V2M_LAN9118		(V2M_PA_CS3 + 0x02000000)
75*cd4f46e1SRyan Harkin #define V2M_ISP1761		(V2M_PA_CS3 + 0x03000000)
76*cd4f46e1SRyan Harkin 
77*cd4f46e1SRyan Harkin /* Common peripherals relative to CS7. */
78*cd4f46e1SRyan Harkin #define V2M_AACI		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
79*cd4f46e1SRyan Harkin #define V2M_MMCI		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
80*cd4f46e1SRyan Harkin #define V2M_KMI0		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
81*cd4f46e1SRyan Harkin #define V2M_KMI1		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
82*cd4f46e1SRyan Harkin 
83*cd4f46e1SRyan Harkin #define V2M_UART0		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
84*cd4f46e1SRyan Harkin #define V2M_UART1		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
85*cd4f46e1SRyan Harkin #define V2M_UART2		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
86*cd4f46e1SRyan Harkin #define V2M_UART3		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
87*cd4f46e1SRyan Harkin 
88*cd4f46e1SRyan Harkin #define V2M_WDT			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
89*cd4f46e1SRyan Harkin 
90*cd4f46e1SRyan Harkin #define V2M_TIMER01		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
91*cd4f46e1SRyan Harkin #define V2M_TIMER23		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
92*cd4f46e1SRyan Harkin 
93*cd4f46e1SRyan Harkin #define V2M_SERIAL_BUS_DVI	(V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
94*cd4f46e1SRyan Harkin #define V2M_RTC			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
95*cd4f46e1SRyan Harkin 
96*cd4f46e1SRyan Harkin #define V2M_CF			(V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
97*cd4f46e1SRyan Harkin 
98*cd4f46e1SRyan Harkin #define V2M_CLCD		(V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
99*cd4f46e1SRyan Harkin #define V2M_SIZE_CS7		V2M_PERIPH_OFFSET(32)
100*cd4f46e1SRyan Harkin 
101*cd4f46e1SRyan Harkin /* System register offsets. */
102*cd4f46e1SRyan Harkin #define V2M_SYS_CFGDATA		(V2M_SYSREGS + 0x0a0)
103*cd4f46e1SRyan Harkin #define V2M_SYS_CFGCTRL		(V2M_SYSREGS + 0x0a4)
104*cd4f46e1SRyan Harkin #define V2M_SYS_CFGSTAT		(V2M_SYSREGS + 0x0a8)
105*cd4f46e1SRyan Harkin 
106*cd4f46e1SRyan Harkin /*
107*cd4f46e1SRyan Harkin  * Configuration
108*cd4f46e1SRyan Harkin  */
109*cd4f46e1SRyan Harkin #define SYS_CFG_START		(1 << 31)
110*cd4f46e1SRyan Harkin #define SYS_CFG_WRITE		(1 << 30)
111*cd4f46e1SRyan Harkin #define SYS_CFG_OSC		(1 << 20)
112*cd4f46e1SRyan Harkin #define SYS_CFG_VOLT		(2 << 20)
113*cd4f46e1SRyan Harkin #define SYS_CFG_AMP		(3 << 20)
114*cd4f46e1SRyan Harkin #define SYS_CFG_TEMP		(4 << 20)
115*cd4f46e1SRyan Harkin #define SYS_CFG_RESET		(5 << 20)
116*cd4f46e1SRyan Harkin #define SYS_CFG_SCC		(6 << 20)
117*cd4f46e1SRyan Harkin #define SYS_CFG_MUXFPGA		(7 << 20)
118*cd4f46e1SRyan Harkin #define SYS_CFG_SHUTDOWN	(8 << 20)
119*cd4f46e1SRyan Harkin #define SYS_CFG_REBOOT		(9 << 20)
120*cd4f46e1SRyan Harkin #define SYS_CFG_DVIMODE		(11 << 20)
121*cd4f46e1SRyan Harkin #define SYS_CFG_POWER		(12 << 20)
122*cd4f46e1SRyan Harkin #define SYS_CFG_SITE_MB		(0 << 16)
123*cd4f46e1SRyan Harkin #define SYS_CFG_SITE_DB1	(1 << 16)
124*cd4f46e1SRyan Harkin #define SYS_CFG_SITE_DB2	(2 << 16)
125*cd4f46e1SRyan Harkin #define SYS_CFG_STACK(n)	((n) << 12)
126*cd4f46e1SRyan Harkin 
127*cd4f46e1SRyan Harkin #define SYS_CFG_ERR		(1 << 1)
128*cd4f46e1SRyan Harkin #define SYS_CFG_COMPLETE	(1 << 0)
1299b58a3f6SRyan Harkin 
1309b58a3f6SRyan Harkin /* Board info register */
131*cd4f46e1SRyan Harkin #define SYS_ID				V2M_SYSREGS
1329b58a3f6SRyan Harkin #define CONFIG_REVISION_TAG		1
1339b58a3f6SRyan Harkin 
134*cd4f46e1SRyan Harkin #define CONFIG_SYS_MEMTEST_START	V2M_BASE
1359b58a3f6SRyan Harkin #define CONFIG_SYS_MEMTEST_END		0x20000000
1369b58a3f6SRyan Harkin #define CONFIG_SYS_HZ			1000
1379b58a3f6SRyan Harkin 
1389b58a3f6SRyan Harkin #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
1399b58a3f6SRyan Harkin #define CONFIG_SETUP_MEMORY_TAGS	1
1409b58a3f6SRyan Harkin #define CONFIG_SYS_L2CACHE_OFF		1
1419b58a3f6SRyan Harkin #define CONFIG_INITRD_TAG		1
1429b58a3f6SRyan Harkin 
1439b58a3f6SRyan Harkin #define CONFIG_OF_LIBFDT		1
1449b58a3f6SRyan Harkin 
1459b58a3f6SRyan Harkin /* Size of malloc() pool */
1469b58a3f6SRyan Harkin #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
1479b58a3f6SRyan Harkin 
148*cd4f46e1SRyan Harkin #define SCTL_BASE			V2M_SYSCTL
1499b58a3f6SRyan Harkin #define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
1509b58a3f6SRyan Harkin 
1519b58a3f6SRyan Harkin /* SMSC9115 Ethernet from SMSC9118 family */
1529b58a3f6SRyan Harkin #define CONFIG_SMC911X			1
1539b58a3f6SRyan Harkin #define CONFIG_SMC911X_32_BIT		1
154*cd4f46e1SRyan Harkin #define CONFIG_SMC911X_BASE		V2M_LAN9118
1559b58a3f6SRyan Harkin 
1569b58a3f6SRyan Harkin /* PL011 Serial Configuration */
1579b58a3f6SRyan Harkin #define CONFIG_PL011_SERIAL
1589b58a3f6SRyan Harkin #define CONFIG_PL011_CLOCK		24000000
1599b58a3f6SRyan Harkin #define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
1609b58a3f6SRyan Harkin 					 (void *)CONFIG_SYS_SERIAL1}
1619b58a3f6SRyan Harkin #define CONFIG_CONS_INDEX		0
1629b58a3f6SRyan Harkin 
1639b58a3f6SRyan Harkin #define CONFIG_BAUDRATE			38400
164*cd4f46e1SRyan Harkin #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
165*cd4f46e1SRyan Harkin #define CONFIG_SYS_SERIAL0		V2M_UART0
166*cd4f46e1SRyan Harkin #define CONFIG_SYS_SERIAL1		V2M_UART1
1679b58a3f6SRyan Harkin 
1689b58a3f6SRyan Harkin /* Command line configuration */
1699b58a3f6SRyan Harkin #define CONFIG_CMD_BDI
1709b58a3f6SRyan Harkin #define CONFIG_CMD_DHCP
1719b58a3f6SRyan Harkin #define CONFIG_CMD_PXE
1729b58a3f6SRyan Harkin #define CONFIG_MENU
1739b58a3f6SRyan Harkin #define CONFIG_CMD_ELF
1749b58a3f6SRyan Harkin #define CONFIG_CMD_ENV
1759b58a3f6SRyan Harkin #define CONFIG_CMD_FLASH
1769b58a3f6SRyan Harkin #define CONFIG_CMD_IMI
1779b58a3f6SRyan Harkin #define CONFIG_CMD_MEMORY
1789b58a3f6SRyan Harkin #define CONFIG_CMD_NET
1799b58a3f6SRyan Harkin #define CONFIG_CMD_PING
1809b58a3f6SRyan Harkin #define CONFIG_CMD_SAVEENV
1819b58a3f6SRyan Harkin #define CONFIG_CMD_RUN
1829b58a3f6SRyan Harkin 
1839b58a3f6SRyan Harkin #define CONFIG_CMD_FAT
1849b58a3f6SRyan Harkin #define CONFIG_DOS_PARTITION		1
1859b58a3f6SRyan Harkin #define CONFIG_MMC			1
1869b58a3f6SRyan Harkin #define CONFIG_CMD_MMC
1879b58a3f6SRyan Harkin #define CONFIG_GENERIC_MMC
1889b58a3f6SRyan Harkin #define CONFIG_ARM_PL180_MMCI
189*cd4f46e1SRyan Harkin #define CONFIG_ARM_PL180_MMCI_BASE	V2M_MMCI
1909b58a3f6SRyan Harkin #define CONFIG_SYS_MMC_MAX_BLK_COUNT	127
1919b58a3f6SRyan Harkin #define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
1929b58a3f6SRyan Harkin 
1939b58a3f6SRyan Harkin /* BOOTP options */
1949b58a3f6SRyan Harkin #define CONFIG_BOOTP_BOOTFILESIZE
1959b58a3f6SRyan Harkin #define CONFIG_BOOTP_BOOTPATH
1969b58a3f6SRyan Harkin #define CONFIG_BOOTP_GATEWAY
1979b58a3f6SRyan Harkin #define CONFIG_BOOTP_HOSTNAME
1989b58a3f6SRyan Harkin #define CONFIG_BOOTP_PXE
1999b58a3f6SRyan Harkin #define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
2009b58a3f6SRyan Harkin 
2019b58a3f6SRyan Harkin /* Miscellaneous configurable options */
2029b58a3f6SRyan Harkin #undef	CONFIG_SYS_CLKS_IN_HZ
203*cd4f46e1SRyan Harkin #define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x8000)
204*cd4f46e1SRyan Harkin #define LINUX_BOOT_PARAM_ADDR		(V2M_BASE + 0x2000)
2059b58a3f6SRyan Harkin #define CONFIG_BOOTDELAY		2
2069b58a3f6SRyan Harkin 
2079b58a3f6SRyan Harkin /* Physical Memory Map */
2089b58a3f6SRyan Harkin #define CONFIG_NR_DRAM_BANKS		2
209*cd4f46e1SRyan Harkin #define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
210*cd4f46e1SRyan Harkin #define PHYS_SDRAM_2			(((unsigned int)V2M_BASE) + \
211*cd4f46e1SRyan Harkin 					((unsigned int)0x20000000))
2129b58a3f6SRyan Harkin #define PHYS_SDRAM_1_SIZE		0x20000000	/* 512 MB */
2139b58a3f6SRyan Harkin #define PHYS_SDRAM_2_SIZE		0x20000000	/* 512 MB */
2149b58a3f6SRyan Harkin 
2159b58a3f6SRyan Harkin /* additions for new relocation code */
2169b58a3f6SRyan Harkin #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
2179b58a3f6SRyan Harkin #define CONFIG_SYS_INIT_RAM_SIZE		0x1000
2189b58a3f6SRyan Harkin #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_SDRAM_BASE + \
2199b58a3f6SRyan Harkin 					 CONFIG_SYS_INIT_RAM_SIZE - \
2209b58a3f6SRyan Harkin 					 GENERATED_GBL_DATA_SIZE)
2219b58a3f6SRyan Harkin #define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_GBL_DATA_OFFSET
2229b58a3f6SRyan Harkin 
2239b58a3f6SRyan Harkin /* Basic environment settings */
2249b58a3f6SRyan Harkin #define CONFIG_BOOTCOMMAND		"run bootflash;"
225*cd4f46e1SRyan Harkin #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
226*cd4f46e1SRyan Harkin #define CONFIG_PLATFORM_ENV_SETTINGS \
2279b58a3f6SRyan Harkin 		"loadaddr=0x80008000\0" \
2289b58a3f6SRyan Harkin 		"ramdisk_addr_r=0x61000000\0" \
2299b58a3f6SRyan Harkin 		"kernel_addr=0x44100000\0" \
2309b58a3f6SRyan Harkin 		"ramdisk_addr=0x44800000\0" \
2319b58a3f6SRyan Harkin 		"maxramdisk=0x1800000\0" \
2329b58a3f6SRyan Harkin 		"pxefile_addr_r=0x88000000\0" \
233*cd4f46e1SRyan Harkin 		"kernel_addr_r=0x80008000\0"
234*cd4f46e1SRyan Harkin #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
235*cd4f46e1SRyan Harkin #define CONFIG_PLATFORM_ENV_SETTINGS \
236*cd4f46e1SRyan Harkin 		"loadaddr=0xa0008000\0" \
237*cd4f46e1SRyan Harkin 		"ramdisk_addr_r=0x81000000\0" \
238*cd4f46e1SRyan Harkin 		"kernel_addr=0x0c100000\0" \
239*cd4f46e1SRyan Harkin 		"ramdisk_addr=0x0c800000\0" \
240*cd4f46e1SRyan Harkin 		"maxramdisk=0x1800000\0" \
241*cd4f46e1SRyan Harkin 		"pxefile_addr_r=0xa8000000\0" \
242*cd4f46e1SRyan Harkin 		"kernel_addr_r=0xa0008000\0"
243*cd4f46e1SRyan Harkin #endif
244*cd4f46e1SRyan Harkin #define CONFIG_EXTRA_ENV_SETTINGS \
245*cd4f46e1SRyan Harkin 		CONFIG_PLATFORM_ENV_SETTINGS \
2469b58a3f6SRyan Harkin 		"console=ttyAMA0,38400n8\0" \
2479b58a3f6SRyan Harkin 		"dram=1024M\0" \
2489b58a3f6SRyan Harkin 		"root=/dev/sda1 rw\0" \
2499b58a3f6SRyan Harkin 		"mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
2509b58a3f6SRyan Harkin 			"24M@0x2000000(initrd)\0" \
2519b58a3f6SRyan Harkin 		"flashargs=setenv bootargs root=${root} console=${console} " \
2529b58a3f6SRyan Harkin 			"mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
2539b58a3f6SRyan Harkin 			"devtmpfs.mount=0  vmalloc=256M\0" \
2549b58a3f6SRyan Harkin 		"bootflash=run flashargs; " \
2559b58a3f6SRyan Harkin 			"cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
2569b58a3f6SRyan Harkin 			"bootm ${kernel_addr} ${ramdisk_addr_r}\0"
2579b58a3f6SRyan Harkin 
2589b58a3f6SRyan Harkin /* FLASH and environment organization */
2599b58a3f6SRyan Harkin #define PHYS_FLASH_SIZE			0x04000000	/* 64MB */
2609b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_CFI		1
2619b58a3f6SRyan Harkin #define CONFIG_FLASH_CFI_DRIVER		1
2629b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_SIZE		0x04000000
2639b58a3f6SRyan Harkin #define CONFIG_SYS_MAX_FLASH_BANKS	2
264*cd4f46e1SRyan Harkin #define CONFIG_SYS_FLASH_BASE0		V2M_NOR0
265*cd4f46e1SRyan Harkin #define CONFIG_SYS_FLASH_BASE1		V2M_NOR1
2669b58a3f6SRyan Harkin #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE0
2679b58a3f6SRyan Harkin 
2689b58a3f6SRyan Harkin /* Timeout values in ticks */
2699b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_ERASE_TOUT	(2 * CONFIG_SYS_HZ) /* Erase Timeout */
2709b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_WRITE_TOUT	(2 * CONFIG_SYS_HZ) /* Write Timeout */
2719b58a3f6SRyan Harkin 
2729b58a3f6SRyan Harkin /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
2739b58a3f6SRyan Harkin #define CONFIG_SYS_MAX_FLASH_SECT	259		/* Max sectors */
2749b58a3f6SRyan Harkin #define FLASH_MAX_SECTOR_SIZE		0x00040000	/* 256 KB sectors */
2759b58a3f6SRyan Harkin 
2769b58a3f6SRyan Harkin /* Room required on the stack for the environment data */
2779b58a3f6SRyan Harkin #define CONFIG_ENV_SIZE			FLASH_MAX_SECTOR_SIZE
2789b58a3f6SRyan Harkin 
2799b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
2809b58a3f6SRyan Harkin 
2819b58a3f6SRyan Harkin /*
2829b58a3f6SRyan Harkin  * Amount of flash used for environment:
2839b58a3f6SRyan Harkin  * We don't know which end has the small erase blocks so we use the penultimate
2849b58a3f6SRyan Harkin  * sector location for the environment
2859b58a3f6SRyan Harkin  */
2869b58a3f6SRyan Harkin #define CONFIG_ENV_SECT_SIZE		FLASH_MAX_SECTOR_SIZE
2879b58a3f6SRyan Harkin #define CONFIG_ENV_OVERWRITE		1
2889b58a3f6SRyan Harkin 
2899b58a3f6SRyan Harkin /* Store environment at top of flash */
2909b58a3f6SRyan Harkin #define CONFIG_ENV_IS_IN_FLASH		1
2919b58a3f6SRyan Harkin #define CONFIG_ENV_OFFSET		(PHYS_FLASH_SIZE - \
2929b58a3f6SRyan Harkin 					(2 * CONFIG_ENV_SECT_SIZE))
2939b58a3f6SRyan Harkin #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE1 + \
2949b58a3f6SRyan Harkin 					 CONFIG_ENV_OFFSET)
2959b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
2969b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
2979b58a3f6SRyan Harkin #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE0, \
2989b58a3f6SRyan Harkin 					  CONFIG_SYS_FLASH_BASE1 }
2999b58a3f6SRyan Harkin 
3009b58a3f6SRyan Harkin /* Monitor Command Prompt */
3019b58a3f6SRyan Harkin #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
3029b58a3f6SRyan Harkin #define CONFIG_SYS_PROMPT		"VExpress# "
3039b58a3f6SRyan Harkin #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
3049b58a3f6SRyan Harkin 					sizeof(CONFIG_SYS_PROMPT) + 16)
3059b58a3f6SRyan Harkin #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
3069b58a3f6SRyan Harkin #define CONFIG_CMD_SOURCE
3079b58a3f6SRyan Harkin #define CONFIG_SYS_LONGHELP
3089b58a3f6SRyan Harkin #define CONFIG_CMDLINE_EDITING		1
3099b58a3f6SRyan Harkin #define CONFIG_SYS_MAXARGS		16	/* max command args */
3109b58a3f6SRyan Harkin 
311*cd4f46e1SRyan Harkin #endif /* VEXPRESS_COMMON_H */
312