1 /* 2 * Configuration for Versatile Express. Parts were derived from other ARM 3 * configurations. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __VEXPRESS_AEMV8A_H 9 #define __VEXPRESS_AEMV8A_H 10 11 /* We use generic board for v8 Versatile Express */ 12 #define CONFIG_SYS_GENERIC_BOARD 13 14 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 15 #ifndef CONFIG_SEMIHOSTING 16 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING 17 #endif 18 #define CONFIG_BOARD_LATE_INIT 19 #define CONFIG_ARMV8_SWITCH_TO_EL1 20 #endif 21 22 #define CONFIG_REMAKE_ELF 23 24 #if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \ 25 !defined(CONFIG_TARGET_VEXPRESS64_JUNO) 26 /* Base FVP and Juno not using GICv3 yet */ 27 #define CONFIG_GICV3 28 #endif 29 30 /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ 31 32 #define CONFIG_SUPPORT_RAW_INITRD 33 34 /* Cache Definitions */ 35 #define CONFIG_SYS_DCACHE_OFF 36 #define CONFIG_SYS_ICACHE_OFF 37 38 #define CONFIG_IDENT_STRING " vexpress_aemv8a" 39 #define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" 40 41 /* Link Definitions */ 42 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 43 /* ATF loads u-boot here for BASE_FVP model */ 44 #define CONFIG_SYS_TEXT_BASE 0x88000000 45 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) 46 #elif CONFIG_TARGET_VEXPRESS64_JUNO 47 #define CONFIG_SYS_TEXT_BASE 0xe0000000 48 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 49 #else 50 #define CONFIG_SYS_TEXT_BASE 0x80000000 51 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 52 #endif 53 54 /* Flat Device Tree Definitions */ 55 #define CONFIG_OF_LIBFDT 56 57 /* SMP Spin Table Definitions */ 58 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 59 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) 60 #else 61 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 62 #endif 63 64 /* CS register bases for the original memory map. */ 65 #define V2M_PA_CS0 0x00000000 66 #define V2M_PA_CS1 0x14000000 67 #define V2M_PA_CS2 0x18000000 68 #define V2M_PA_CS3 0x1c000000 69 #define V2M_PA_CS4 0x0c000000 70 #define V2M_PA_CS5 0x10000000 71 72 #define V2M_PERIPH_OFFSET(x) (x << 16) 73 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) 74 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) 75 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) 76 77 #define V2M_BASE 0x80000000 78 79 /* Common peripherals relative to CS7. */ 80 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) 81 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) 82 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) 83 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) 84 85 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 86 #define V2M_UART0 0x7ff80000 87 #define V2M_UART1 0x7ff70000 88 #else /* Not Juno */ 89 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) 90 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) 91 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) 92 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) 93 #endif 94 95 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) 96 97 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) 98 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) 99 100 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) 101 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) 102 103 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) 104 105 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) 106 107 /* System register offsets. */ 108 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) 109 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) 110 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) 111 112 /* Generic Timer Definitions */ 113 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 114 115 /* Generic Interrupt Controller Definitions */ 116 #ifdef CONFIG_GICV3 117 #define GICD_BASE (0x2f000000) 118 #define GICR_BASE (0x2f100000) 119 #else 120 121 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 122 #define GICD_BASE (0x2f000000) 123 #define GICC_BASE (0x2c000000) 124 #elif CONFIG_TARGET_VEXPRESS64_JUNO 125 #define GICD_BASE (0x2C010000) 126 #define GICC_BASE (0x2C02f000) 127 #else 128 #define GICD_BASE (0x2C001000) 129 #define GICC_BASE (0x2C002000) 130 #endif 131 #endif 132 133 #define CONFIG_SYS_MEMTEST_START V2M_BASE 134 #define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) 135 136 /* Size of malloc() pool */ 137 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) 138 139 /* Ethernet Configuration */ 140 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 141 /* The real hardware Versatile express uses SMSC9118 */ 142 #define CONFIG_SMC911X 1 143 #define CONFIG_SMC911X_32_BIT 1 144 #define CONFIG_SMC911X_BASE (0x018000000) 145 #else 146 /* The Vexpress64 simulators use SMSC91C111 */ 147 #define CONFIG_SMC91111 1 148 #define CONFIG_SMC91111_BASE (0x01A000000) 149 #endif 150 151 /* PL011 Serial Configuration */ 152 #define CONFIG_PL011_SERIAL 153 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 154 #define CONFIG_PL011_CLOCK 7273800 155 #else 156 #define CONFIG_PL011_CLOCK 24000000 157 #endif 158 #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ 159 (void *)CONFIG_SYS_SERIAL1} 160 #define CONFIG_CONS_INDEX 0 161 162 #define CONFIG_BAUDRATE 115200 163 #define CONFIG_SYS_SERIAL0 V2M_UART0 164 #define CONFIG_SYS_SERIAL1 V2M_UART1 165 166 /* Command line configuration */ 167 #define CONFIG_MENU 168 /*#define CONFIG_MENU_SHOW*/ 169 #define CONFIG_CMD_CACHE 170 #define CONFIG_CMD_BDI 171 #define CONFIG_CMD_BOOTI 172 #define CONFIG_CMD_UNZIP 173 #define CONFIG_CMD_DHCP 174 #define CONFIG_CMD_PXE 175 #define CONFIG_CMD_ENV 176 #define CONFIG_CMD_IMI 177 #define CONFIG_CMD_LOADB 178 #define CONFIG_CMD_MEMORY 179 #define CONFIG_CMD_MII 180 #define CONFIG_CMD_NET 181 #define CONFIG_CMD_PING 182 #define CONFIG_CMD_SAVEENV 183 #define CONFIG_CMD_RUN 184 #define CONFIG_CMD_BOOTD 185 #define CONFIG_CMD_ECHO 186 #define CONFIG_CMD_SOURCE 187 #define CONFIG_CMD_FAT 188 #define CONFIG_DOS_PARTITION 189 190 /* BOOTP options */ 191 #define CONFIG_BOOTP_BOOTFILESIZE 192 #define CONFIG_BOOTP_BOOTPATH 193 #define CONFIG_BOOTP_GATEWAY 194 #define CONFIG_BOOTP_HOSTNAME 195 #define CONFIG_BOOTP_PXE 196 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 197 198 /* Miscellaneous configurable options */ 199 #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) 200 201 /* Physical Memory Map */ 202 #define CONFIG_NR_DRAM_BANKS 1 203 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ 204 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2048 MB */ 205 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 206 207 /* Initial environment variables */ 208 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 209 #define CONFIG_EXTRA_ENV_SETTINGS \ 210 "kernel_name=uImage\0" \ 211 "kernel_addr_r=0x80000000\0" \ 212 "initrd_name=ramdisk.img\0" \ 213 "initrd_addr_r=0x88000000\0" \ 214 "fdt_name=devtree.dtb\0" \ 215 "fdt_addr_r=0x83000000\0" \ 216 "fdt_high=0xffffffffffffffff\0" \ 217 "initrd_high=0xffffffffffffffff\0" 218 219 #define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ 220 "0x1c090000 debug user_debug=31 "\ 221 "loglevel=9" 222 223 #define CONFIG_BOOTCOMMAND "fdt addr $fdt_addr_r; fdt resize; " \ 224 "fdt chosen $initrd_addr_r $initrd_end; " \ 225 "bootm $kernel_addr_r - $fdt_addr_r" 226 227 #define CONFIG_BOOTDELAY 1 228 229 #else 230 231 #define CONFIG_EXTRA_ENV_SETTINGS \ 232 "kernel_addr_r=0x80000000\0" \ 233 "initrd_addr_r=0x88000000\0" \ 234 "fdt_addr_r=0x83000000\0" \ 235 "fdt_high=0xa0000000\0" 236 237 #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/ram0" 238 #define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \ 239 "$initrd_addr_r:$initrd_size $fdt_addr_r" 240 #define CONFIG_BOOTDELAY -1 241 #endif 242 243 /* Do not preserve environment */ 244 #define CONFIG_ENV_IS_NOWHERE 1 245 #define CONFIG_ENV_SIZE 0x1000 246 247 /* Monitor Command Prompt */ 248 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 249 #define CONFIG_SYS_PROMPT "VExpress64# " 250 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 251 sizeof(CONFIG_SYS_PROMPT) + 16) 252 #define CONFIG_SYS_HUSH_PARSER 253 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 254 #define CONFIG_SYS_LONGHELP 255 #define CONFIG_CMDLINE_EDITING 256 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 257 258 /* Flash memory is available on the Juno board only */ 259 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO 260 #define CONFIG_SYS_NO_FLASH 261 #else 262 #define CONFIG_CMD_FLASH 263 #define CONFIG_SYS_FLASH_CFI 1 264 #define CONFIG_FLASH_CFI_DRIVER 1 265 #define CONFIG_SYS_FLASH_BASE 0x08000000 266 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */ 267 #define CONFIG_SYS_MAX_FLASH_BANKS 2 268 269 /* Timeout values in ticks */ 270 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ 271 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ 272 273 /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ 274 #define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ 275 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ 276 #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ 277 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 278 279 #endif 280 281 #endif /* __VEXPRESS_AEMV8A_H */ 282