1 /* 2 * Configuration for Versatile Express. Parts were derived from other ARM 3 * configurations. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __VEXPRESS_AEMV8A_H 9 #define __VEXPRESS_AEMV8A_H 10 11 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 12 #ifndef CONFIG_SEMIHOSTING 13 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING 14 #endif 15 #define CONFIG_ARMV8_SWITCH_TO_EL1 16 #endif 17 18 #define CONFIG_REMAKE_ELF 19 20 #define CONFIG_SUPPORT_RAW_INITRD 21 22 /* Link Definitions */ 23 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ 24 defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) 25 /* ATF loads u-boot here for BASE_FVP model */ 26 #define CONFIG_SYS_TEXT_BASE 0x88000000 27 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) 28 #elif CONFIG_TARGET_VEXPRESS64_JUNO 29 #define CONFIG_SYS_TEXT_BASE 0xe0000000 30 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 31 #endif 32 33 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 34 35 /* CS register bases for the original memory map. */ 36 #define V2M_PA_CS0 0x00000000 37 #define V2M_PA_CS1 0x14000000 38 #define V2M_PA_CS2 0x18000000 39 #define V2M_PA_CS3 0x1c000000 40 #define V2M_PA_CS4 0x0c000000 41 #define V2M_PA_CS5 0x10000000 42 43 #define V2M_PERIPH_OFFSET(x) (x << 16) 44 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) 45 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) 46 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) 47 48 #define V2M_BASE 0x80000000 49 50 /* Common peripherals relative to CS7. */ 51 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) 52 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) 53 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) 54 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) 55 56 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 57 #define V2M_UART0 0x7ff80000 58 #define V2M_UART1 0x7ff70000 59 #else /* Not Juno */ 60 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) 61 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) 62 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) 63 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) 64 #endif 65 66 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) 67 68 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) 69 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) 70 71 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) 72 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) 73 74 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) 75 76 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) 77 78 /* System register offsets. */ 79 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) 80 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) 81 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) 82 83 /* Generic Timer Definitions */ 84 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 85 86 /* Generic Interrupt Controller Definitions */ 87 #ifdef CONFIG_GICV3 88 #define GICD_BASE (0x2f000000) 89 #define GICR_BASE (0x2f100000) 90 #else 91 92 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ 93 defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) 94 #define GICD_BASE (0x2f000000) 95 #define GICC_BASE (0x2c000000) 96 #elif CONFIG_TARGET_VEXPRESS64_JUNO 97 #define GICD_BASE (0x2C010000) 98 #define GICC_BASE (0x2C02f000) 99 #endif 100 #endif /* !CONFIG_GICV3 */ 101 102 /* Size of malloc() pool */ 103 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) 104 105 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO 106 /* The Vexpress64 simulators use SMSC91C111 */ 107 #define CONFIG_SMC91111 1 108 #define CONFIG_SMC91111_BASE (0x01A000000) 109 #endif 110 111 /* PL011 Serial Configuration */ 112 #define CONFIG_CONS_INDEX 0 113 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 114 #define CONFIG_PL011_CLOCK 7273800 115 #else 116 #define CONFIG_PL011_CLOCK 24000000 117 #endif 118 119 /*#define CONFIG_MENU_SHOW*/ 120 121 /* BOOTP options */ 122 #define CONFIG_BOOTP_BOOTFILESIZE 123 #define CONFIG_BOOTP_BOOTPATH 124 #define CONFIG_BOOTP_GATEWAY 125 #define CONFIG_BOOTP_HOSTNAME 126 #define CONFIG_BOOTP_PXE 127 128 /* Miscellaneous configurable options */ 129 #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) 130 131 /* Physical Memory Map */ 132 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ 133 /* Top 16MB reserved for secure world use */ 134 #define DRAM_SEC_SIZE 0x01000000 135 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE 136 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 137 138 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 139 #define CONFIG_NR_DRAM_BANKS 2 140 #define PHYS_SDRAM_2 (0x880000000) 141 #define PHYS_SDRAM_2_SIZE 0x180000000 142 #else 143 #define CONFIG_NR_DRAM_BANKS 1 144 #endif 145 146 /* Enable memtest */ 147 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 148 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) 149 150 /* Initial environment variables */ 151 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 152 /* 153 * Defines where the kernel and FDT exist in NOR flash and where it will 154 * be copied into DRAM 155 */ 156 #define CONFIG_EXTRA_ENV_SETTINGS \ 157 "kernel_name=norkern\0" \ 158 "kernel_alt_name=Image\0" \ 159 "kernel_addr=0x80080000\0" \ 160 "initrd_name=ramdisk.img\0" \ 161 "initrd_addr=0x84000000\0" \ 162 "fdtfile=board.dtb\0" \ 163 "fdt_alt_name=juno\0" \ 164 "fdt_addr=0x83000000\0" \ 165 "fdt_high=0xffffffffffffffff\0" \ 166 "initrd_high=0xffffffffffffffff\0" \ 167 168 /* Copy the kernel and FDT to DRAM memory and boot */ 169 #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ 170 "if test $? -eq 1; then "\ 171 " echo Loading ${kernel_alt_name} instead of "\ 172 "${kernel_name}; "\ 173 " afs load ${kernel_alt_name} ${kernel_addr};"\ 174 "fi ; "\ 175 "afs load ${fdtfile} ${fdt_addr} ; " \ 176 "if test $? -eq 1; then "\ 177 " echo Loading ${fdt_alt_name} instead of "\ 178 "${fdtfile}; "\ 179 " afs load ${fdt_alt_name} ${fdt_addr}; "\ 180 "fi ; "\ 181 "fdt addr ${fdt_addr}; fdt resize; " \ 182 "if afs load ${initrd_name} ${initrd_addr} ; "\ 183 "then "\ 184 " setenv initrd_param ${initrd_addr}; "\ 185 " else setenv initrd_param -; "\ 186 "fi ; " \ 187 "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" 188 189 190 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP 191 #define CONFIG_EXTRA_ENV_SETTINGS \ 192 "kernel_name=Image\0" \ 193 "kernel_addr=0x80080000\0" \ 194 "initrd_name=ramdisk.img\0" \ 195 "initrd_addr=0x88000000\0" \ 196 "fdtfile=devtree.dtb\0" \ 197 "fdt_addr=0x83000000\0" \ 198 "fdt_high=0xffffffffffffffff\0" \ 199 "initrd_high=0xffffffffffffffff\0" 200 201 #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ 202 "smhload ${fdtfile} ${fdt_addr}; " \ 203 "smhload ${initrd_name} ${initrd_addr} "\ 204 "initrd_end; " \ 205 "fdt addr ${fdt_addr}; fdt resize; " \ 206 "fdt chosen ${initrd_addr} ${initrd_end}; " \ 207 "booti $kernel_addr - $fdt_addr" 208 209 210 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM 211 #define CONFIG_EXTRA_ENV_SETTINGS \ 212 "kernel_addr=0x80080000\0" \ 213 "initrd_addr=0x84000000\0" \ 214 "fdt_addr=0x83000000\0" \ 215 "fdt_high=0xffffffffffffffff\0" \ 216 "initrd_high=0xffffffffffffffff\0" 217 218 #define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" 219 220 221 #endif 222 223 /* Monitor Command Prompt */ 224 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 225 #define CONFIG_SYS_LONGHELP 226 #define CONFIG_CMDLINE_EDITING 227 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 228 229 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 230 #define CONFIG_SYS_FLASH_BASE 0x08000000 231 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ 232 #define CONFIG_SYS_MAX_FLASH_SECT 259 233 /* Store environment at top of flash in the same location as blank.img */ 234 /* in the Juno firmware. */ 235 #define CONFIG_ENV_ADDR 0x0BFC0000 236 #define CONFIG_ENV_SECT_SIZE 0x00010000 237 #else 238 #define CONFIG_SYS_FLASH_BASE 0x0C000000 239 /* 256 x 256KiB sectors */ 240 #define CONFIG_SYS_MAX_FLASH_SECT 256 241 /* Store environment at top of flash */ 242 #define CONFIG_ENV_ADDR 0x0FFC0000 243 #define CONFIG_ENV_SECT_SIZE 0x00040000 244 #endif 245 246 #define CONFIG_SYS_FLASH_CFI 1 247 #define CONFIG_FLASH_CFI_DRIVER 1 248 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 249 #define CONFIG_SYS_MAX_FLASH_BANKS 1 250 251 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ 252 #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ 253 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 254 #define FLASH_MAX_SECTOR_SIZE 0x00040000 255 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 256 257 #endif /* __VEXPRESS_AEMV8A_H */ 258