1 /*
2  * Configuration for Versatile Express. Parts were derived from other ARM
3  *   configurations.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __VEXPRESS_AEMV8A_H
9 #define __VEXPRESS_AEMV8A_H
10 
11 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
12 #ifndef CONFIG_SEMIHOSTING
13 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
14 #endif
15 #define CONFIG_ARMV8_SWITCH_TO_EL1
16 #endif
17 
18 #define CONFIG_REMAKE_ELF
19 
20 #define CONFIG_SUPPORT_RAW_INITRD
21 
22 /* Link Definitions */
23 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
24 	defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
25 /* ATF loads u-boot here for BASE_FVP model */
26 #define CONFIG_SYS_TEXT_BASE		0x88000000
27 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
28 #elif CONFIG_TARGET_VEXPRESS64_JUNO
29 #define CONFIG_SYS_TEXT_BASE		0xe0000000
30 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
31 #endif
32 
33 #define CONFIG_SYS_BOOTM_LEN (64 << 20)      /* Increase max gunzip size */
34 
35 /* CS register bases for the original memory map. */
36 #define V2M_PA_CS0			0x00000000
37 #define V2M_PA_CS1			0x14000000
38 #define V2M_PA_CS2			0x18000000
39 #define V2M_PA_CS3			0x1c000000
40 #define V2M_PA_CS4			0x0c000000
41 #define V2M_PA_CS5			0x10000000
42 
43 #define V2M_PERIPH_OFFSET(x)		(x << 16)
44 #define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
45 #define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
46 #define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
47 
48 #define V2M_BASE			0x80000000
49 
50 /* Common peripherals relative to CS7. */
51 #define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
52 #define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
53 #define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
54 #define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
55 
56 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
57 #define V2M_UART0			0x7ff80000
58 #define V2M_UART1			0x7ff70000
59 #else /* Not Juno */
60 #define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
61 #define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
62 #define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
63 #define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
64 #endif
65 
66 #define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
67 
68 #define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
69 #define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
70 
71 #define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
72 #define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
73 
74 #define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
75 
76 #define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
77 
78 /* System register offsets. */
79 #define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
80 #define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
81 #define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)
82 
83 /* Generic Timer Definitions */
84 #define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
85 
86 /* Generic Interrupt Controller Definitions */
87 #ifdef CONFIG_GICV3
88 #define GICD_BASE			(0x2f000000)
89 #define GICR_BASE			(0x2f100000)
90 #else
91 
92 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
93 	defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM)
94 #define GICD_BASE			(0x2f000000)
95 #define GICC_BASE			(0x2c000000)
96 #elif CONFIG_TARGET_VEXPRESS64_JUNO
97 #define GICD_BASE			(0x2C010000)
98 #define GICC_BASE			(0x2C02f000)
99 #endif
100 #endif /* !CONFIG_GICV3 */
101 
102 /* Size of malloc() pool */
103 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))
104 
105 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO
106 /* The Vexpress64 simulators use SMSC91C111 */
107 #define CONFIG_SMC91111			1
108 #define CONFIG_SMC91111_BASE		(0x01A000000)
109 #endif
110 
111 /* PL011 Serial Configuration */
112 #define CONFIG_CONS_INDEX		0
113 #define CONFIG_PL01X_SERIAL
114 #define CONFIG_PL011_SERIAL
115 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
116 #define CONFIG_PL011_CLOCK		7273800
117 #else
118 #define CONFIG_PL011_CLOCK		24000000
119 #endif
120 
121 /*#define CONFIG_MENU_SHOW*/
122 
123 /* BOOTP options */
124 #define CONFIG_BOOTP_BOOTFILESIZE
125 #define CONFIG_BOOTP_BOOTPATH
126 #define CONFIG_BOOTP_GATEWAY
127 #define CONFIG_BOOTP_HOSTNAME
128 #define CONFIG_BOOTP_PXE
129 
130 /* Miscellaneous configurable options */
131 #define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)
132 
133 /* Physical Memory Map */
134 #define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
135 /* Top 16MB reserved for secure world use */
136 #define DRAM_SEC_SIZE		0x01000000
137 #define PHYS_SDRAM_1_SIZE	0x80000000 - DRAM_SEC_SIZE
138 #define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
139 
140 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
141 #define CONFIG_NR_DRAM_BANKS		2
142 #define PHYS_SDRAM_2			(0x880000000)
143 #define PHYS_SDRAM_2_SIZE		0x180000000
144 #else
145 #define CONFIG_NR_DRAM_BANKS		1
146 #endif
147 
148 /* Enable memtest */
149 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
150 #define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
151 
152 /* Initial environment variables */
153 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
154 /*
155  * Defines where the kernel and FDT exist in NOR flash and where it will
156  * be copied into DRAM
157  */
158 #define CONFIG_EXTRA_ENV_SETTINGS	\
159 				"kernel_name=norkern\0"	\
160 				"kernel_alt_name=Image\0"	\
161 				"kernel_addr=0x80080000\0" \
162 				"initrd_name=ramdisk.img\0"	\
163 				"initrd_addr=0x84000000\0"	\
164 				"fdtfile=board.dtb\0" \
165 				"fdt_alt_name=juno\0" \
166 				"fdt_addr=0x83000000\0" \
167 				"fdt_high=0xffffffffffffffff\0" \
168 				"initrd_high=0xffffffffffffffff\0" \
169 
170 /* Copy the kernel and FDT to DRAM memory and boot */
171 #define CONFIG_BOOTCOMMAND	"afs load ${kernel_name} ${kernel_addr} ; " \
172 				"if test $? -eq 1; then "\
173 				"  echo Loading ${kernel_alt_name} instead of "\
174 				"${kernel_name}; "\
175 				"  afs load ${kernel_alt_name} ${kernel_addr};"\
176 				"fi ; "\
177 				"afs load  ${fdtfile} ${fdt_addr} ; " \
178 				"if test $? -eq 1; then "\
179 				"  echo Loading ${fdt_alt_name} instead of "\
180 				"${fdtfile}; "\
181 				"  afs load ${fdt_alt_name} ${fdt_addr}; "\
182 				"fi ; "\
183 				"fdt addr ${fdt_addr}; fdt resize; " \
184 				"if afs load  ${initrd_name} ${initrd_addr} ; "\
185 				"then "\
186 				"  setenv initrd_param ${initrd_addr}; "\
187 				"  else setenv initrd_param -; "\
188 				"fi ; " \
189 				"booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
190 
191 
192 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
193 #define CONFIG_EXTRA_ENV_SETTINGS	\
194 				"kernel_name=Image\0"		\
195 				"kernel_addr=0x80080000\0"	\
196 				"initrd_name=ramdisk.img\0"	\
197 				"initrd_addr=0x88000000\0"	\
198 				"fdtfile=devtree.dtb\0"		\
199 				"fdt_addr=0x83000000\0"		\
200 				"fdt_high=0xffffffffffffffff\0"	\
201 				"initrd_high=0xffffffffffffffff\0"
202 
203 #define CONFIG_BOOTCOMMAND	"smhload ${kernel_name} ${kernel_addr}; " \
204 				"smhload ${fdtfile} ${fdt_addr}; " \
205 				"smhload ${initrd_name} ${initrd_addr} "\
206 				"initrd_end; " \
207 				"fdt addr ${fdt_addr}; fdt resize; " \
208 				"fdt chosen ${initrd_addr} ${initrd_end}; " \
209 				"booti $kernel_addr - $fdt_addr"
210 
211 
212 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM
213 #define CONFIG_EXTRA_ENV_SETTINGS	\
214 				"kernel_addr=0x80080000\0"	\
215 				"initrd_addr=0x84000000\0"	\
216 				"fdt_addr=0x83000000\0"		\
217 				"fdt_high=0xffffffffffffffff\0"	\
218 				"initrd_high=0xffffffffffffffff\0"
219 
220 #define CONFIG_BOOTCOMMAND	"booti $kernel_addr $initrd_addr $fdt_addr"
221 
222 
223 #endif
224 
225 /* Monitor Command Prompt */
226 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
227 #define CONFIG_SYS_LONGHELP
228 #define CONFIG_CMDLINE_EDITING
229 #define CONFIG_SYS_MAXARGS		64	/* max command args */
230 
231 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
232 #define CONFIG_SYS_FLASH_BASE		0x08000000
233 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
234 #define CONFIG_SYS_MAX_FLASH_SECT	259
235 /* Store environment at top of flash in the same location as blank.img */
236 /* in the Juno firmware. */
237 #define CONFIG_ENV_ADDR			0x0BFC0000
238 #define CONFIG_ENV_SECT_SIZE		0x00010000
239 #else
240 #define CONFIG_SYS_FLASH_BASE		0x0C000000
241 /* 256 x 256KiB sectors */
242 #define CONFIG_SYS_MAX_FLASH_SECT	256
243 /* Store environment at top of flash */
244 #define CONFIG_ENV_ADDR			0x0FFC0000
245 #define CONFIG_ENV_SECT_SIZE		0x00040000
246 #endif
247 
248 #define CONFIG_SYS_FLASH_CFI		1
249 #define CONFIG_FLASH_CFI_DRIVER		1
250 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
251 #define CONFIG_SYS_MAX_FLASH_BANKS	1
252 
253 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
254 #define CONFIG_SYS_FLASH_PROTECTION	/* The devices have real protection */
255 #define CONFIG_SYS_FLASH_EMPTY_INFO	/* flinfo indicates empty blocks */
256 #define FLASH_MAX_SECTOR_SIZE		0x00040000
257 #define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
258 
259 #endif /* __VEXPRESS_AEMV8A_H */
260