1 /*
2  * Configuration for Versatile Express. Parts were derived from other ARM
3  *   configurations.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __VEXPRESS_AEMV8A_H
9 #define __VEXPRESS_AEMV8A_H
10 
11 #define DEBUG
12 
13 #define CONFIG_REMAKE_ELF
14 
15 /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
16 
17 /*#define CONFIG_SYS_GENERIC_BOARD*/
18 
19 #define CONFIG_SYS_NO_FLASH
20 
21 #define CONFIG_SUPPORT_RAW_INITRD
22 
23 /* Cache Definitions */
24 #define CONFIG_SYS_DCACHE_OFF
25 #define CONFIG_SYS_ICACHE_OFF
26 
27 #define CONFIG_IDENT_STRING		" vexpress_aemv8a"
28 #define CONFIG_BOOTP_VCI_STRING		"U-boot.armv8.vexpress_aemv8a"
29 
30 /* Link Definitions */
31 #define CONFIG_SYS_TEXT_BASE		0x80000000
32 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
33 
34 /* Flat Device Tree Definitions */
35 #define CONFIG_OF_LIBFDT
36 
37 #define CONFIG_DEFAULT_DEVICE_TREE	vexpress64
38 
39 /* SMP Spin Table Definitions */
40 #define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
41 
42 /* CS register bases for the original memory map. */
43 #define V2M_PA_CS0			0x00000000
44 #define V2M_PA_CS1			0x14000000
45 #define V2M_PA_CS2			0x18000000
46 #define V2M_PA_CS3			0x1c000000
47 #define V2M_PA_CS4			0x0c000000
48 #define V2M_PA_CS5			0x10000000
49 
50 #define V2M_PERIPH_OFFSET(x)		(x << 16)
51 #define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
52 #define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
53 #define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
54 
55 #define V2M_BASE			0x80000000
56 
57 /*
58  * Physical addresses, offset from V2M_PA_CS0-3
59  */
60 #define V2M_NOR0			(V2M_PA_CS0)
61 #define V2M_NOR1			(V2M_PA_CS4)
62 #define V2M_SRAM			(V2M_PA_CS1)
63 
64 /* Common peripherals relative to CS7. */
65 #define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
66 #define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
67 #define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
68 #define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
69 
70 #define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
71 #define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
72 #define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
73 #define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
74 
75 #define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
76 
77 #define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
78 #define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
79 
80 #define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
81 #define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
82 
83 #define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
84 
85 #define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
86 
87 /* System register offsets. */
88 #define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
89 #define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
90 #define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)
91 
92 /* Generic Timer Definitions */
93 #define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
94 
95 /* Generic Interrupt Controller Definitions */
96 #define GICD_BASE			(0x2C001000)
97 #define GICC_BASE			(0x2C002000)
98 
99 #define CONFIG_SYS_MEMTEST_START	V2M_BASE
100 #define CONFIG_SYS_MEMTEST_END		(V2M_BASE + 0x80000000)
101 
102 /* Size of malloc() pool */
103 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
104 
105 /* SMSC91C111 Ethernet Configuration */
106 #define CONFIG_SMC91111			1
107 #define CONFIG_SMC91111_BASE		(0x01A000000)
108 
109 /* PL011 Serial Configuration */
110 #define CONFIG_PL011_SERIAL
111 #define CONFIG_PL011_CLOCK		24000000
112 #define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
113 					 (void *)CONFIG_SYS_SERIAL1}
114 #define CONFIG_CONS_INDEX		0
115 
116 #define CONFIG_BAUDRATE			115200
117 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
118 #define CONFIG_SYS_SERIAL0		V2M_UART0
119 #define CONFIG_SYS_SERIAL1		V2M_UART1
120 
121 /* Command line configuration */
122 #define CONFIG_MENU
123 /*#define CONFIG_MENU_SHOW*/
124 #define CONFIG_CMD_CACHE
125 #define CONFIG_CMD_BDI
126 #define CONFIG_CMD_DHCP
127 #define CONFIG_CMD_PXE
128 #define CONFIG_CMD_ENV
129 #define CONFIG_CMD_FLASH
130 #define CONFIG_CMD_IMI
131 #define CONFIG_CMD_MEMORY
132 #define CONFIG_CMD_MII
133 #define CONFIG_CMD_NET
134 #define CONFIG_CMD_PING
135 #define CONFIG_CMD_SAVEENV
136 #define CONFIG_CMD_RUN
137 #define CONFIG_CMD_BOOTD
138 #define CONFIG_CMD_ECHO
139 #define CONFIG_CMD_SOURCE
140 #define CONFIG_CMD_FAT
141 #define CONFIG_DOS_PARTITION
142 
143 /* BOOTP options */
144 #define CONFIG_BOOTP_BOOTFILESIZE
145 #define CONFIG_BOOTP_BOOTPATH
146 #define CONFIG_BOOTP_GATEWAY
147 #define CONFIG_BOOTP_HOSTNAME
148 #define CONFIG_BOOTP_PXE
149 #define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
150 
151 /* Miscellaneous configurable options */
152 #define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)
153 
154 /* Physical Memory Map */
155 #define CONFIG_NR_DRAM_BANKS		1
156 #define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
157 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2048 MB */
158 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
159 
160 /* Initial environment variables */
161 #define CONFIG_EXTRA_ENV_SETTINGS	\
162 					"kernel_addr=0x200000\0"	\
163 					"initrd_addr=0xa00000\0"	\
164 					"initrd_size=0x2000000\0"	\
165 					"fdt_addr=0x100000\0"		\
166 					"fdt_high=0xa0000000\0"
167 
168 #define CONFIG_BOOTARGS			"console=ttyAMA0 root=/dev/ram0"
169 #define CONFIG_BOOTCOMMAND		"bootm $kernel_addr " \
170 					"$initrd_addr:$initrd_size $fdt_addr"
171 #define CONFIG_BOOTDELAY		-1
172 
173 /* Do not preserve environment */
174 #define CONFIG_ENV_IS_NOWHERE		1
175 #define CONFIG_ENV_SIZE			0x1000
176 
177 /* Monitor Command Prompt */
178 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
179 #define CONFIG_SYS_PROMPT		"VExpress64# "
180 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
181 					sizeof(CONFIG_SYS_PROMPT) + 16)
182 #define CONFIG_SYS_HUSH_PARSER
183 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
184 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
185 #define CONFIG_SYS_LONGHELP
186 #define CONFIG_CMDLINE_EDITING		1
187 #define CONFIG_SYS_MAXARGS		64	/* max command args */
188 
189 #endif /* __VEXPRESS_AEMV8A_H */
190