1 /*
2  * Configuration for Versatile Express. Parts were derived from other ARM
3  *   configurations.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __VEXPRESS_AEMV8A_H
9 #define __VEXPRESS_AEMV8A_H
10 
11 /* We use generic board for v8 Versatile Express */
12 #define CONFIG_SYS_GENERIC_BOARD
13 
14 #ifdef CONFIG_BASE_FVP
15 #ifndef CONFIG_SEMIHOSTING
16 #error CONFIG_BASE_FVP requires CONFIG_SEMIHOSTING
17 #endif
18 #define CONFIG_BOARD_LATE_INIT
19 #define CONFIG_ARMV8_SWITCH_TO_EL1
20 #endif
21 
22 #define CONFIG_REMAKE_ELF
23 
24 #ifndef CONFIG_BASE_FVP
25 /* Base FVP not using GICv3 yet */
26 #define CONFIG_GICV3
27 #endif
28 
29 /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
30 
31 #define CONFIG_SYS_NO_FLASH
32 
33 #define CONFIG_SUPPORT_RAW_INITRD
34 
35 /* Cache Definitions */
36 #define CONFIG_SYS_DCACHE_OFF
37 #define CONFIG_SYS_ICACHE_OFF
38 
39 #define CONFIG_IDENT_STRING		" vexpress_aemv8a"
40 #define CONFIG_BOOTP_VCI_STRING		"U-boot.armv8.vexpress_aemv8a"
41 
42 /* Link Definitions */
43 #ifdef CONFIG_BASE_FVP
44 /* ATF loads u-boot here for BASE_FVP model */
45 #define CONFIG_SYS_TEXT_BASE		0x88000000
46 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
47 #else
48 #define CONFIG_SYS_TEXT_BASE		0x80000000
49 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
50 #endif
51 
52 /* Flat Device Tree Definitions */
53 #define CONFIG_OF_LIBFDT
54 
55 
56 /* SMP Spin Table Definitions */
57 #ifdef CONFIG_BASE_FVP
58 #define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x03f00000)
59 #else
60 #define CPU_RELEASE_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fff0)
61 #endif
62 
63 /* CS register bases for the original memory map. */
64 #define V2M_PA_CS0			0x00000000
65 #define V2M_PA_CS1			0x14000000
66 #define V2M_PA_CS2			0x18000000
67 #define V2M_PA_CS3			0x1c000000
68 #define V2M_PA_CS4			0x0c000000
69 #define V2M_PA_CS5			0x10000000
70 
71 #define V2M_PERIPH_OFFSET(x)		(x << 16)
72 #define V2M_SYSREGS			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
73 #define V2M_SYSCTL			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
74 #define V2M_SERIAL_BUS_PCI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
75 
76 #define V2M_BASE			0x80000000
77 
78 /*
79  * Physical addresses, offset from V2M_PA_CS0-3
80  */
81 #define V2M_NOR0			(V2M_PA_CS0)
82 #define V2M_NOR1			(V2M_PA_CS4)
83 #define V2M_SRAM			(V2M_PA_CS1)
84 
85 /* Common peripherals relative to CS7. */
86 #define V2M_AACI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
87 #define V2M_MMCI			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
88 #define V2M_KMI0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
89 #define V2M_KMI1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
90 
91 #define V2M_UART0			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
92 #define V2M_UART1			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
93 #define V2M_UART2			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
94 #define V2M_UART3			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
95 
96 #define V2M_WDT				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
97 
98 #define V2M_TIMER01			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
99 #define V2M_TIMER23			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
100 
101 #define V2M_SERIAL_BUS_DVI		(V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
102 #define V2M_RTC				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
103 
104 #define V2M_CF				(V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
105 
106 #define V2M_CLCD			(V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
107 
108 /* System register offsets. */
109 #define V2M_SYS_CFGDATA			(V2M_SYSREGS + 0x0a0)
110 #define V2M_SYS_CFGCTRL			(V2M_SYSREGS + 0x0a4)
111 #define V2M_SYS_CFGSTAT			(V2M_SYSREGS + 0x0a8)
112 
113 /* Generic Timer Definitions */
114 #define COUNTER_FREQUENCY		(0x1800000)	/* 24MHz */
115 
116 /* Generic Interrupt Controller Definitions */
117 #ifdef CONFIG_GICV3
118 #define GICD_BASE			(0x2f000000)
119 #define GICR_BASE			(0x2f100000)
120 #else
121 
122 #ifdef CONFIG_BASE_FVP
123 #define GICD_BASE			(0x2f000000)
124 #define GICC_BASE			(0x2c000000)
125 #else
126 #define GICD_BASE			(0x2C001000)
127 #define GICC_BASE			(0x2C002000)
128 #endif
129 #endif
130 
131 #define CONFIG_SYS_MEMTEST_START	V2M_BASE
132 #define CONFIG_SYS_MEMTEST_END		(V2M_BASE + 0x80000000)
133 
134 /* Size of malloc() pool */
135 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 << 20))
136 
137 /* SMSC91C111 Ethernet Configuration */
138 #define CONFIG_SMC91111			1
139 #define CONFIG_SMC91111_BASE		(0x01A000000)
140 
141 /* PL011 Serial Configuration */
142 #define CONFIG_PL011_SERIAL
143 #define CONFIG_PL011_CLOCK		24000000
144 #define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
145 					 (void *)CONFIG_SYS_SERIAL1}
146 #define CONFIG_CONS_INDEX		0
147 
148 #define CONFIG_BAUDRATE			115200
149 #define CONFIG_SYS_SERIAL0		V2M_UART0
150 #define CONFIG_SYS_SERIAL1		V2M_UART1
151 
152 /* Command line configuration */
153 #define CONFIG_MENU
154 /*#define CONFIG_MENU_SHOW*/
155 #define CONFIG_CMD_CACHE
156 #define CONFIG_CMD_BDI
157 #define CONFIG_CMD_BOOTI
158 #define CONFIG_CMD_UNZIP
159 #define CONFIG_CMD_DHCP
160 #define CONFIG_CMD_PXE
161 #define CONFIG_CMD_ENV
162 #define CONFIG_CMD_FLASH
163 #define CONFIG_CMD_IMI
164 #define CONFIG_CMD_MEMORY
165 #define CONFIG_CMD_MII
166 #define CONFIG_CMD_NET
167 #define CONFIG_CMD_PING
168 #define CONFIG_CMD_SAVEENV
169 #define CONFIG_CMD_RUN
170 #define CONFIG_CMD_BOOTD
171 #define CONFIG_CMD_ECHO
172 #define CONFIG_CMD_SOURCE
173 #define CONFIG_CMD_FAT
174 #define CONFIG_DOS_PARTITION
175 
176 /* BOOTP options */
177 #define CONFIG_BOOTP_BOOTFILESIZE
178 #define CONFIG_BOOTP_BOOTPATH
179 #define CONFIG_BOOTP_GATEWAY
180 #define CONFIG_BOOTP_HOSTNAME
181 #define CONFIG_BOOTP_PXE
182 #define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
183 
184 /* Miscellaneous configurable options */
185 #define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)
186 
187 /* Physical Memory Map */
188 #define CONFIG_NR_DRAM_BANKS		1
189 #define PHYS_SDRAM_1			(V2M_BASE)	/* SDRAM Bank #1 */
190 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2048 MB */
191 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
192 
193 /* Initial environment variables */
194 #ifdef CONFIG_BASE_FVP
195 #define CONFIG_EXTRA_ENV_SETTINGS	\
196 				"kernel_name=uImage\0"	\
197 				"kernel_addr_r=0x80000000\0"	\
198 				"initrd_name=ramdisk.img\0"	\
199 				"initrd_addr_r=0x88000000\0"	\
200 				"fdt_name=devtree.dtb\0"		\
201 				"fdt_addr_r=0x83000000\0"		\
202 				"fdt_high=0xffffffffffffffff\0"	\
203 				"initrd_high=0xffffffffffffffff\0"
204 
205 #define CONFIG_BOOTARGS		"console=ttyAMA0 earlyprintk=pl011,"\
206 				"0x1c090000 debug user_debug=31 "\
207 				"loglevel=9"
208 
209 #define CONFIG_BOOTCOMMAND	"fdt addr $fdt_addr_r; fdt resize; " \
210 				"fdt chosen $initrd_addr_r $initrd_end; " \
211 				"bootm $kernel_addr_r - $fdt_addr_r"
212 
213 #define CONFIG_BOOTDELAY		1
214 
215 #else
216 
217 #define CONFIG_EXTRA_ENV_SETTINGS	\
218 					"kernel_addr_r=0x80000000\0"	\
219 					"initrd_addr_r=0x88000000\0"	\
220 					"fdt_addr_r=0x83000000\0"		\
221 					"fdt_high=0xa0000000\0"
222 
223 #define CONFIG_BOOTARGS			"console=ttyAMA0 root=/dev/ram0"
224 #define CONFIG_BOOTCOMMAND		"bootm $kernel_addr_r " \
225 					"$initrd_addr_r:$initrd_size $fdt_addr_r"
226 #define CONFIG_BOOTDELAY		-1
227 #endif
228 
229 /* Do not preserve environment */
230 #define CONFIG_ENV_IS_NOWHERE		1
231 #define CONFIG_ENV_SIZE			0x1000
232 
233 /* Monitor Command Prompt */
234 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
235 #define CONFIG_SYS_PROMPT		"VExpress64# "
236 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
237 					sizeof(CONFIG_SYS_PROMPT) + 16)
238 #define CONFIG_SYS_HUSH_PARSER
239 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
240 #define CONFIG_SYS_LONGHELP
241 #define CONFIG_CMDLINE_EDITING
242 #define CONFIG_SYS_MAXARGS		64	/* max command args */
243 
244 #endif /* __VEXPRESS_AEMV8A_H */
245