1 /* 2 * Configuration for Versatile Express. Parts were derived from other ARM 3 * configurations. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __VEXPRESS_AEMV8A_H 9 #define __VEXPRESS_AEMV8A_H 10 11 /* We use generic board and device manager for v8 Versatile Express */ 12 #define CONFIG_SYS_GENERIC_BOARD 13 14 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 15 #ifndef CONFIG_SEMIHOSTING 16 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING 17 #endif 18 #define CONFIG_ARMV8_SWITCH_TO_EL1 19 #endif 20 21 #define CONFIG_REMAKE_ELF 22 23 #define CONFIG_SUPPORT_RAW_INITRD 24 25 /* Cache Definitions */ 26 #define CONFIG_SYS_DCACHE_OFF 27 #define CONFIG_SYS_ICACHE_OFF 28 29 #define CONFIG_IDENT_STRING " vexpress_aemv8a" 30 #define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" 31 32 /* Link Definitions */ 33 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 34 /* ATF loads u-boot here for BASE_FVP model */ 35 #define CONFIG_SYS_TEXT_BASE 0x88000000 36 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) 37 #elif CONFIG_TARGET_VEXPRESS64_JUNO 38 #define CONFIG_SYS_TEXT_BASE 0xe0000000 39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 40 #else 41 #error "Unknown board variant" 42 #endif 43 44 /* Flat Device Tree Definitions */ 45 #define CONFIG_OF_LIBFDT 46 47 /* CS register bases for the original memory map. */ 48 #define V2M_PA_CS0 0x00000000 49 #define V2M_PA_CS1 0x14000000 50 #define V2M_PA_CS2 0x18000000 51 #define V2M_PA_CS3 0x1c000000 52 #define V2M_PA_CS4 0x0c000000 53 #define V2M_PA_CS5 0x10000000 54 55 #define V2M_PERIPH_OFFSET(x) (x << 16) 56 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) 57 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) 58 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) 59 60 #define V2M_BASE 0x80000000 61 62 /* Common peripherals relative to CS7. */ 63 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) 64 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) 65 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) 66 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) 67 68 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 69 #define V2M_UART0 0x7ff80000 70 #define V2M_UART1 0x7ff70000 71 #else /* Not Juno */ 72 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) 73 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) 74 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) 75 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) 76 #endif 77 78 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) 79 80 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) 81 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) 82 83 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) 84 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) 85 86 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) 87 88 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) 89 90 /* System register offsets. */ 91 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) 92 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) 93 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) 94 95 /* Generic Timer Definitions */ 96 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 97 98 /* Generic Interrupt Controller Definitions */ 99 #ifdef CONFIG_GICV3 100 #define GICD_BASE (0x2f000000) 101 #define GICR_BASE (0x2f100000) 102 #else 103 104 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 105 #define GICD_BASE (0x2f000000) 106 #define GICC_BASE (0x2c000000) 107 #elif CONFIG_TARGET_VEXPRESS64_JUNO 108 #define GICD_BASE (0x2C010000) 109 #define GICC_BASE (0x2C02f000) 110 #else 111 #error "Unknown board variant" 112 #endif 113 #endif /* !CONFIG_GICV3 */ 114 115 /* Size of malloc() pool */ 116 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) 117 118 /* Ethernet Configuration */ 119 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 120 /* The real hardware Versatile express uses SMSC9118 */ 121 #define CONFIG_SMC911X 1 122 #define CONFIG_SMC911X_32_BIT 1 123 #define CONFIG_SMC911X_BASE (0x018000000) 124 #else 125 /* The Vexpress64 simulators use SMSC91C111 */ 126 #define CONFIG_SMC91111 1 127 #define CONFIG_SMC91111_BASE (0x01A000000) 128 #endif 129 130 /* PL011 Serial Configuration */ 131 #define CONFIG_BAUDRATE 115200 132 #define CONFIG_CONS_INDEX 0 133 #define CONFIG_PL01X_SERIAL 134 #define CONFIG_PL011_SERIAL 135 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 136 #define CONFIG_PL011_CLOCK 7273800 137 #else 138 #define CONFIG_PL011_CLOCK 24000000 139 #endif 140 141 /* Command line configuration */ 142 #define CONFIG_MENU 143 /*#define CONFIG_MENU_SHOW*/ 144 #define CONFIG_CMD_CACHE 145 #define CONFIG_CMD_BOOTI 146 #define CONFIG_CMD_UNZIP 147 #define CONFIG_CMD_DHCP 148 #define CONFIG_CMD_PXE 149 #define CONFIG_CMD_ENV 150 #define CONFIG_CMD_MII 151 #define CONFIG_CMD_PING 152 #define CONFIG_CMD_FAT 153 #define CONFIG_DOS_PARTITION 154 155 /* BOOTP options */ 156 #define CONFIG_BOOTP_BOOTFILESIZE 157 #define CONFIG_BOOTP_BOOTPATH 158 #define CONFIG_BOOTP_GATEWAY 159 #define CONFIG_BOOTP_HOSTNAME 160 #define CONFIG_BOOTP_PXE 161 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 162 163 /* Miscellaneous configurable options */ 164 #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) 165 166 /* Physical Memory Map */ 167 #define CONFIG_NR_DRAM_BANKS 1 168 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ 169 /* Top 16MB reserved for secure world use */ 170 #define DRAM_SEC_SIZE 0x01000000 171 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE 172 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 173 174 /* Enable memtest */ 175 #define CONFIG_CMD_MEMTEST 176 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 177 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) 178 179 /* Initial environment variables */ 180 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 181 /* 182 * Defines where the kernel and FDT exist in NOR flash and where it will 183 * be copied into DRAM 184 */ 185 #define CONFIG_EXTRA_ENV_SETTINGS \ 186 "kernel_name=Image\0" \ 187 "kernel_addr=0x80000000\0" \ 188 "fdt_name=juno\0" \ 189 "fdt_addr=0x83000000\0" \ 190 "fdt_high=0xffffffffffffffff\0" \ 191 "initrd_high=0xffffffffffffffff\0" \ 192 193 /* Assume we boot with root on the first partition of a USB stick */ 194 #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 " \ 195 "root=/dev/sda1 rw " \ 196 "rootwait "\ 197 "earlyprintk=pl011,0x7ff80000 debug user_debug=31 "\ 198 "loglevel=9" 199 200 /* Copy the kernel and FDT to DRAM memory and boot */ 201 #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ 202 "afs load ${fdt_name} ${fdt_addr} ; " \ 203 "fdt addr ${fdt_addr}; fdt resize; " \ 204 "booti ${kernel_addr} - ${fdt_addr}" 205 206 #define CONFIG_BOOTDELAY 1 207 208 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP 209 #define CONFIG_EXTRA_ENV_SETTINGS \ 210 "kernel_name=Image\0" \ 211 "kernel_addr=0x80000000\0" \ 212 "initrd_name=ramdisk.img\0" \ 213 "initrd_addr=0x88000000\0" \ 214 "fdt_name=devtree.dtb\0" \ 215 "fdt_addr=0x83000000\0" \ 216 "fdt_high=0xffffffffffffffff\0" \ 217 "initrd_high=0xffffffffffffffff\0" 218 219 #define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ 220 "0x1c090000 debug user_debug=31 "\ 221 "loglevel=9" 222 223 #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ 224 "smhload ${fdt_name} ${fdt_addr}; " \ 225 "smhload ${initrd_name} ${initrd_addr} initrd_end; " \ 226 "fdt addr ${fdt_addr}; fdt resize; " \ 227 "fdt chosen ${initrd_addr} ${initrd_end}; " \ 228 "booti $kernel_addr - $fdt_addr" 229 230 #define CONFIG_BOOTDELAY 1 231 232 #else 233 #error "Unknown board variant" 234 #endif 235 236 /* Do not preserve environment */ 237 #define CONFIG_ENV_IS_NOWHERE 1 238 #define CONFIG_ENV_SIZE 0x1000 239 240 /* Monitor Command Prompt */ 241 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 242 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 243 sizeof(CONFIG_SYS_PROMPT) + 16) 244 #define CONFIG_SYS_HUSH_PARSER 245 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 246 #define CONFIG_SYS_LONGHELP 247 #define CONFIG_CMDLINE_EDITING 248 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 249 250 /* Flash memory is available on the Juno board only */ 251 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO 252 #define CONFIG_SYS_NO_FLASH 253 #else 254 #define CONFIG_CMD_ARMFLASH 255 #define CONFIG_SYS_FLASH_CFI 1 256 #define CONFIG_FLASH_CFI_DRIVER 1 257 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 258 #define CONFIG_SYS_FLASH_BASE 0x08000000 259 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */ 260 #define CONFIG_SYS_MAX_FLASH_BANKS 2 261 262 /* Timeout values in ticks */ 263 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ 264 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ 265 266 /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ 267 #define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ 268 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ 269 #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ 270 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 271 272 #endif 273 274 #endif /* __VEXPRESS_AEMV8A_H */ 275