1 /* 2 * Configuration for Versatile Express. Parts were derived from other ARM 3 * configurations. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __VEXPRESS_AEMV8A_H 9 #define __VEXPRESS_AEMV8A_H 10 11 /* We use generic board for v8 Versatile Express */ 12 #define CONFIG_SYS_GENERIC_BOARD 13 14 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 15 #ifndef CONFIG_SEMIHOSTING 16 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING 17 #endif 18 #define CONFIG_BOARD_LATE_INIT 19 #define CONFIG_ARMV8_SWITCH_TO_EL1 20 #endif 21 22 #define CONFIG_REMAKE_ELF 23 24 #if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \ 25 !defined(CONFIG_TARGET_VEXPRESS64_JUNO) 26 /* Base FVP and Juno not using GICv3 yet */ 27 #define CONFIG_GICV3 28 #endif 29 30 /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/ 31 32 #define CONFIG_SUPPORT_RAW_INITRD 33 34 /* Cache Definitions */ 35 #define CONFIG_SYS_DCACHE_OFF 36 #define CONFIG_SYS_ICACHE_OFF 37 38 #define CONFIG_IDENT_STRING " vexpress_aemv8a" 39 #define CONFIG_BOOTP_VCI_STRING "U-boot.armv8.vexpress_aemv8a" 40 41 /* Link Definitions */ 42 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 43 /* ATF loads u-boot here for BASE_FVP model */ 44 #define CONFIG_SYS_TEXT_BASE 0x88000000 45 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) 46 #elif CONFIG_TARGET_VEXPRESS64_JUNO 47 #define CONFIG_SYS_TEXT_BASE 0xe0000000 48 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 49 #else 50 #define CONFIG_SYS_TEXT_BASE 0x80000000 51 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 52 #endif 53 54 /* Flat Device Tree Definitions */ 55 #define CONFIG_OF_LIBFDT 56 57 /* CS register bases for the original memory map. */ 58 #define V2M_PA_CS0 0x00000000 59 #define V2M_PA_CS1 0x14000000 60 #define V2M_PA_CS2 0x18000000 61 #define V2M_PA_CS3 0x1c000000 62 #define V2M_PA_CS4 0x0c000000 63 #define V2M_PA_CS5 0x10000000 64 65 #define V2M_PERIPH_OFFSET(x) (x << 16) 66 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) 67 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) 68 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) 69 70 #define V2M_BASE 0x80000000 71 72 /* Common peripherals relative to CS7. */ 73 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) 74 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) 75 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) 76 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) 77 78 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 79 #define V2M_UART0 0x7ff80000 80 #define V2M_UART1 0x7ff70000 81 #else /* Not Juno */ 82 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) 83 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) 84 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) 85 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) 86 #endif 87 88 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) 89 90 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) 91 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) 92 93 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) 94 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) 95 96 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) 97 98 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) 99 100 /* System register offsets. */ 101 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) 102 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) 103 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) 104 105 /* Generic Timer Definitions */ 106 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 107 108 /* Generic Interrupt Controller Definitions */ 109 #ifdef CONFIG_GICV3 110 #define GICD_BASE (0x2f000000) 111 #define GICR_BASE (0x2f100000) 112 #else 113 114 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 115 #define GICD_BASE (0x2f000000) 116 #define GICC_BASE (0x2c000000) 117 #elif CONFIG_TARGET_VEXPRESS64_JUNO 118 #define GICD_BASE (0x2C010000) 119 #define GICC_BASE (0x2C02f000) 120 #else 121 #define GICD_BASE (0x2C001000) 122 #define GICC_BASE (0x2C002000) 123 #endif 124 #endif 125 126 #define CONFIG_SYS_MEMTEST_START V2M_BASE 127 #define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x80000000) 128 129 /* Size of malloc() pool */ 130 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) 131 132 /* Ethernet Configuration */ 133 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 134 /* The real hardware Versatile express uses SMSC9118 */ 135 #define CONFIG_SMC911X 1 136 #define CONFIG_SMC911X_32_BIT 1 137 #define CONFIG_SMC911X_BASE (0x018000000) 138 #else 139 /* The Vexpress64 simulators use SMSC91C111 */ 140 #define CONFIG_SMC91111 1 141 #define CONFIG_SMC91111_BASE (0x01A000000) 142 #endif 143 144 /* PL011 Serial Configuration */ 145 #define CONFIG_PL011_SERIAL 146 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 147 #define CONFIG_PL011_CLOCK 7273800 148 #else 149 #define CONFIG_PL011_CLOCK 24000000 150 #endif 151 #define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ 152 (void *)CONFIG_SYS_SERIAL1} 153 #define CONFIG_CONS_INDEX 0 154 155 #define CONFIG_BAUDRATE 115200 156 #define CONFIG_SYS_SERIAL0 V2M_UART0 157 #define CONFIG_SYS_SERIAL1 V2M_UART1 158 159 /* Command line configuration */ 160 #define CONFIG_MENU 161 /*#define CONFIG_MENU_SHOW*/ 162 #define CONFIG_CMD_CACHE 163 #define CONFIG_CMD_BDI 164 #define CONFIG_CMD_BOOTI 165 #define CONFIG_CMD_UNZIP 166 #define CONFIG_CMD_DHCP 167 #define CONFIG_CMD_PXE 168 #define CONFIG_CMD_ENV 169 #define CONFIG_CMD_IMI 170 #define CONFIG_CMD_LOADB 171 #define CONFIG_CMD_MEMORY 172 #define CONFIG_CMD_MII 173 #define CONFIG_CMD_NET 174 #define CONFIG_CMD_PING 175 #define CONFIG_CMD_SAVEENV 176 #define CONFIG_CMD_RUN 177 #define CONFIG_CMD_BOOTD 178 #define CONFIG_CMD_ECHO 179 #define CONFIG_CMD_SOURCE 180 #define CONFIG_CMD_FAT 181 #define CONFIG_DOS_PARTITION 182 183 /* BOOTP options */ 184 #define CONFIG_BOOTP_BOOTFILESIZE 185 #define CONFIG_BOOTP_BOOTPATH 186 #define CONFIG_BOOTP_GATEWAY 187 #define CONFIG_BOOTP_HOSTNAME 188 #define CONFIG_BOOTP_PXE 189 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 190 191 /* Miscellaneous configurable options */ 192 #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) 193 194 /* Physical Memory Map */ 195 #define CONFIG_NR_DRAM_BANKS 1 196 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ 197 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2048 MB */ 198 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 199 200 /* Initial environment variables */ 201 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 202 #define CONFIG_EXTRA_ENV_SETTINGS \ 203 "kernel_name=uImage\0" \ 204 "kernel_addr_r=0x80000000\0" \ 205 "initrd_name=ramdisk.img\0" \ 206 "initrd_addr_r=0x88000000\0" \ 207 "fdt_name=devtree.dtb\0" \ 208 "fdt_addr_r=0x83000000\0" \ 209 "fdt_high=0xffffffffffffffff\0" \ 210 "initrd_high=0xffffffffffffffff\0" 211 212 #define CONFIG_BOOTARGS "console=ttyAMA0 earlyprintk=pl011,"\ 213 "0x1c090000 debug user_debug=31 "\ 214 "loglevel=9" 215 216 #define CONFIG_BOOTCOMMAND "fdt addr $fdt_addr_r; fdt resize; " \ 217 "fdt chosen $initrd_addr_r $initrd_end; " \ 218 "bootm $kernel_addr_r - $fdt_addr_r" 219 220 #define CONFIG_BOOTDELAY 1 221 222 #else 223 224 #define CONFIG_EXTRA_ENV_SETTINGS \ 225 "kernel_addr_r=0x80000000\0" \ 226 "initrd_addr_r=0x88000000\0" \ 227 "fdt_addr_r=0x83000000\0" \ 228 "fdt_high=0xa0000000\0" 229 230 #define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 root=/dev/ram0" 231 #define CONFIG_BOOTCOMMAND "bootm $kernel_addr_r " \ 232 "$initrd_addr_r:$initrd_size $fdt_addr_r" 233 #define CONFIG_BOOTDELAY -1 234 #endif 235 236 /* Do not preserve environment */ 237 #define CONFIG_ENV_IS_NOWHERE 1 238 #define CONFIG_ENV_SIZE 0x1000 239 240 /* Monitor Command Prompt */ 241 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 242 #define CONFIG_SYS_PROMPT "VExpress64# " 243 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 244 sizeof(CONFIG_SYS_PROMPT) + 16) 245 #define CONFIG_SYS_HUSH_PARSER 246 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 247 #define CONFIG_SYS_LONGHELP 248 #define CONFIG_CMDLINE_EDITING 249 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 250 251 /* Flash memory is available on the Juno board only */ 252 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO 253 #define CONFIG_SYS_NO_FLASH 254 #else 255 #define CONFIG_CMD_FLASH 256 #define CONFIG_SYS_FLASH_CFI 1 257 #define CONFIG_FLASH_CFI_DRIVER 1 258 #define CONFIG_SYS_FLASH_BASE 0x08000000 259 #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MiB */ 260 #define CONFIG_SYS_MAX_FLASH_BANKS 2 261 262 /* Timeout values in ticks */ 263 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ 264 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ 265 266 /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ 267 #define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ 268 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ 269 #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ 270 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 271 272 #endif 273 274 #endif /* __VEXPRESS_AEMV8A_H */ 275