1 /* 2 * Configuration for Versatile Express. Parts were derived from other ARM 3 * configurations. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __VEXPRESS_AEMV8A_H 9 #define __VEXPRESS_AEMV8A_H 10 11 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP 12 #ifndef CONFIG_SEMIHOSTING 13 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING 14 #endif 15 #define CONFIG_ARMV8_SWITCH_TO_EL1 16 #endif 17 18 #define CONFIG_REMAKE_ELF 19 20 #define CONFIG_SUPPORT_RAW_INITRD 21 22 /* Link Definitions */ 23 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ 24 defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) 25 /* ATF loads u-boot here for BASE_FVP model */ 26 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) 27 #elif CONFIG_TARGET_VEXPRESS64_JUNO 28 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) 29 #endif 30 31 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 32 33 /* CS register bases for the original memory map. */ 34 #define V2M_PA_CS0 0x00000000 35 #define V2M_PA_CS1 0x14000000 36 #define V2M_PA_CS2 0x18000000 37 #define V2M_PA_CS3 0x1c000000 38 #define V2M_PA_CS4 0x0c000000 39 #define V2M_PA_CS5 0x10000000 40 41 #define V2M_PERIPH_OFFSET(x) (x << 16) 42 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) 43 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) 44 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) 45 46 #define V2M_BASE 0x80000000 47 48 /* Common peripherals relative to CS7. */ 49 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) 50 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) 51 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) 52 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) 53 54 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 55 #define V2M_UART0 0x7ff80000 56 #define V2M_UART1 0x7ff70000 57 #else /* Not Juno */ 58 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) 59 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) 60 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) 61 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) 62 #endif 63 64 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) 65 66 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) 67 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) 68 69 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) 70 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) 71 72 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) 73 74 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) 75 76 /* System register offsets. */ 77 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) 78 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) 79 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) 80 81 /* Generic Timer Definitions */ 82 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ 83 84 /* Generic Interrupt Controller Definitions */ 85 #ifdef CONFIG_GICV3 86 #define GICD_BASE (0x2f000000) 87 #define GICR_BASE (0x2f100000) 88 #else 89 90 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ 91 defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM) 92 #define GICD_BASE (0x2f000000) 93 #define GICC_BASE (0x2c000000) 94 #elif CONFIG_TARGET_VEXPRESS64_JUNO 95 #define GICD_BASE (0x2C010000) 96 #define GICC_BASE (0x2C02f000) 97 #endif 98 #endif /* !CONFIG_GICV3 */ 99 100 /* Size of malloc() pool */ 101 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) 102 103 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO 104 /* The Vexpress64 simulators use SMSC91C111 */ 105 #define CONFIG_SMC91111 1 106 #define CONFIG_SMC91111_BASE (0x01A000000) 107 #endif 108 109 /* PL011 Serial Configuration */ 110 #define CONFIG_CONS_INDEX 0 111 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 112 #define CONFIG_PL011_CLOCK 7273800 113 #else 114 #define CONFIG_PL011_CLOCK 24000000 115 #endif 116 117 /*#define CONFIG_MENU_SHOW*/ 118 119 /* BOOTP options */ 120 #define CONFIG_BOOTP_BOOTFILESIZE 121 #define CONFIG_BOOTP_BOOTPATH 122 #define CONFIG_BOOTP_GATEWAY 123 #define CONFIG_BOOTP_HOSTNAME 124 #define CONFIG_BOOTP_PXE 125 126 /* Miscellaneous configurable options */ 127 #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) 128 129 /* Physical Memory Map */ 130 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ 131 /* Top 16MB reserved for secure world use */ 132 #define DRAM_SEC_SIZE 0x01000000 133 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE 134 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 135 136 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 137 #define CONFIG_NR_DRAM_BANKS 2 138 #define PHYS_SDRAM_2 (0x880000000) 139 #define PHYS_SDRAM_2_SIZE 0x180000000 140 #else 141 #define CONFIG_NR_DRAM_BANKS 1 142 #endif 143 144 /* Enable memtest */ 145 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 146 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) 147 148 /* Initial environment variables */ 149 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 150 /* 151 * Defines where the kernel and FDT exist in NOR flash and where it will 152 * be copied into DRAM 153 */ 154 #define CONFIG_EXTRA_ENV_SETTINGS \ 155 "kernel_name=norkern\0" \ 156 "kernel_alt_name=Image\0" \ 157 "kernel_addr=0x80080000\0" \ 158 "initrd_name=ramdisk.img\0" \ 159 "initrd_addr=0x84000000\0" \ 160 "fdtfile=board.dtb\0" \ 161 "fdt_alt_name=juno\0" \ 162 "fdt_addr=0x83000000\0" \ 163 "fdt_high=0xffffffffffffffff\0" \ 164 "initrd_high=0xffffffffffffffff\0" \ 165 166 /* Copy the kernel and FDT to DRAM memory and boot */ 167 #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ 168 "if test $? -eq 1; then "\ 169 " echo Loading ${kernel_alt_name} instead of "\ 170 "${kernel_name}; "\ 171 " afs load ${kernel_alt_name} ${kernel_addr};"\ 172 "fi ; "\ 173 "afs load ${fdtfile} ${fdt_addr} ; " \ 174 "if test $? -eq 1; then "\ 175 " echo Loading ${fdt_alt_name} instead of "\ 176 "${fdtfile}; "\ 177 " afs load ${fdt_alt_name} ${fdt_addr}; "\ 178 "fi ; "\ 179 "fdt addr ${fdt_addr}; fdt resize; " \ 180 "if afs load ${initrd_name} ${initrd_addr} ; "\ 181 "then "\ 182 " setenv initrd_param ${initrd_addr}; "\ 183 " else setenv initrd_param -; "\ 184 "fi ; " \ 185 "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" 186 187 188 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP 189 #define CONFIG_EXTRA_ENV_SETTINGS \ 190 "kernel_name=Image\0" \ 191 "kernel_addr=0x80080000\0" \ 192 "initrd_name=ramdisk.img\0" \ 193 "initrd_addr=0x88000000\0" \ 194 "fdtfile=devtree.dtb\0" \ 195 "fdt_addr=0x83000000\0" \ 196 "fdt_high=0xffffffffffffffff\0" \ 197 "initrd_high=0xffffffffffffffff\0" 198 199 #define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ 200 "smhload ${fdtfile} ${fdt_addr}; " \ 201 "smhload ${initrd_name} ${initrd_addr} "\ 202 "initrd_end; " \ 203 "fdt addr ${fdt_addr}; fdt resize; " \ 204 "fdt chosen ${initrd_addr} ${initrd_end}; " \ 205 "booti $kernel_addr - $fdt_addr" 206 207 208 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM 209 #define CONFIG_EXTRA_ENV_SETTINGS \ 210 "kernel_addr=0x80080000\0" \ 211 "initrd_addr=0x84000000\0" \ 212 "fdt_addr=0x83000000\0" \ 213 "fdt_high=0xffffffffffffffff\0" \ 214 "initrd_high=0xffffffffffffffff\0" 215 216 #define CONFIG_BOOTCOMMAND "booti $kernel_addr $initrd_addr $fdt_addr" 217 218 219 #endif 220 221 /* Monitor Command Prompt */ 222 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 223 #define CONFIG_SYS_LONGHELP 224 #define CONFIG_CMDLINE_EDITING 225 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 226 227 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO 228 #define CONFIG_SYS_FLASH_BASE 0x08000000 229 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ 230 #define CONFIG_SYS_MAX_FLASH_SECT 259 231 /* Store environment at top of flash in the same location as blank.img */ 232 /* in the Juno firmware. */ 233 #define CONFIG_ENV_ADDR 0x0BFC0000 234 #define CONFIG_ENV_SECT_SIZE 0x00010000 235 #else 236 #define CONFIG_SYS_FLASH_BASE 0x0C000000 237 /* 256 x 256KiB sectors */ 238 #define CONFIG_SYS_MAX_FLASH_SECT 256 239 /* Store environment at top of flash */ 240 #define CONFIG_ENV_ADDR 0x0FFC0000 241 #define CONFIG_ENV_SECT_SIZE 0x00040000 242 #endif 243 244 #define CONFIG_SYS_FLASH_CFI 1 245 #define CONFIG_FLASH_CFI_DRIVER 1 246 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 247 #define CONFIG_SYS_MAX_FLASH_BANKS 1 248 249 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */ 250 #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ 251 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 252 #define FLASH_MAX_SECTOR_SIZE 0x00040000 253 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 254 255 #endif /* __VEXPRESS_AEMV8A_H */ 256