1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) Freescale Semiconductor, Inc. 2006. 4 * 5 * (C) Copyright 2010 6 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 7 */ 8 /* 9 * ve8313 board configuration file 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 /* 16 * High Level Configuration Options 17 */ 18 #define CONFIG_E300 1 19 #define CONFIG_MPC831x 1 20 #define CONFIG_MPC8313 1 21 22 #define CONFIG_PCI_INDIRECT_BRIDGE 1 23 #define CONFIG_FSL_ELBC 1 24 25 /* 26 * On-board devices 27 * 28 */ 29 #define CONFIG_83XX_CLKIN 32000000 /* in Hz */ 30 31 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 32 33 #define CONFIG_SYS_IMMR 0xE0000000 34 35 #define CONFIG_SYS_MEMTEST_START 0x00001000 36 #define CONFIG_SYS_MEMTEST_END 0x07000000 37 38 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ 39 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ 40 41 /* 42 * Device configurations 43 */ 44 45 /* 46 * DDR Setup 47 */ 48 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 50 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 51 52 /* 53 * Manually set up DDR parameters, as this board does not 54 * have the SPD connected to I2C. 55 */ 56 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 57 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 58 | CSCONFIG_AP \ 59 | CSCONFIG_ODT_RD_NEVER \ 60 | CSCONFIG_ODT_WR_ALL \ 61 | CSCONFIG_ROW_BIT_13 \ 62 | CSCONFIG_COL_BIT_10) 63 /* 0x80840102 */ 64 65 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 66 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 67 | (0 << TIMING_CFG0_WRT_SHIFT) \ 68 | (3 << TIMING_CFG0_RRT_SHIFT) \ 69 | (2 << TIMING_CFG0_WWT_SHIFT) \ 70 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 71 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 72 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 73 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 74 /* 0x0e720802 */ 75 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 76 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 77 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 78 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 79 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 80 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 81 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 82 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 83 /* 0x26256222 */ 84 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 85 | (5 << TIMING_CFG2_CPO_SHIFT) \ 86 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 87 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 88 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 89 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 90 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 91 /* 0x029028c7 */ 92 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ 93 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 94 /* 0x03202000 */ 95 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 96 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 97 | SDRAM_CFG_DBW_32) 98 /* 0x43080000 */ 99 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 100 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 101 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 102 /* 0x44400232 */ 103 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 104 105 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 106 /*0x02000000*/ 107 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 108 | DDRCDR_PZ_NOMZ \ 109 | DDRCDR_NZ_NOMZ \ 110 | DDRCDR_M_ODR) 111 /* 0x73000002 */ 112 113 /* 114 * FLASH on the Local Bus 115 */ 116 #define CONFIG_SYS_FLASH_BASE 0xFE000000 117 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ 118 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 119 120 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 121 | BR_PS_16 /* 16 bit */ \ 122 | BR_MS_GPCM /* MSEL = GPCM */ \ 123 | BR_V) /* valid */ 124 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 125 | OR_GPCM_CSNT \ 126 | OR_GPCM_ACS_DIV4 \ 127 | OR_GPCM_SCY_5 \ 128 | OR_GPCM_TRLX_SET \ 129 | OR_GPCM_EAD) 130 /* 0xfe000c55 */ 131 132 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 133 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 134 135 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 136 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ 137 138 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 139 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 140 141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 142 143 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 144 #define CONFIG_SYS_RAMBOOT 145 #endif 146 147 #define CONFIG_SYS_INIT_RAM_LOCK 1 148 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 149 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 150 151 #define CONFIG_SYS_GBL_DATA_OFFSET \ 152 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 153 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 154 155 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 156 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 157 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 158 159 /* 160 * Local Bus LCRR and LBCR regs 161 */ 162 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 163 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 164 165 #define CONFIG_SYS_LBC_LBCR 0x00040000 166 167 #define CONFIG_SYS_LBC_MRTPR 0x20000000 168 169 /* 170 * NAND settings 171 */ 172 #define CONFIG_SYS_NAND_BASE 0x61000000 173 #define CONFIG_SYS_MAX_NAND_DEVICE 1 174 #define CONFIG_NAND_FSL_ELBC 1 175 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 176 177 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 178 | BR_PS_8 \ 179 | BR_DECC_CHK_GEN \ 180 | BR_MS_FCM \ 181 | BR_V) /* valid */ 182 /* 0x61000c21 */ 183 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 184 | OR_FCM_BCTLD \ 185 | OR_FCM_CHT \ 186 | OR_FCM_SCY_2 \ 187 | OR_FCM_RST \ 188 | OR_FCM_TRLX) 189 /* 0xffff90ac */ 190 191 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 192 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 193 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 194 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 195 196 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 197 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 198 199 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 200 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 201 202 /* CS2 NvRAM */ 203 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ 204 | BR_PS_8 \ 205 | BR_V) 206 /* 0x60000801 */ 207 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 208 | OR_GPCM_CSNT \ 209 | OR_GPCM_XACS \ 210 | OR_GPCM_SCY_3 \ 211 | OR_GPCM_TRLX_SET \ 212 | OR_GPCM_EHTR_SET \ 213 | OR_GPCM_EAD) 214 /* 0xfffe0937 */ 215 /* local bus read write buffer mapping SRAM@0x64000000 */ 216 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \ 217 | BR_PS_16 \ 218 | BR_V) 219 /* 0x62001001 */ 220 221 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \ 222 | OR_GPCM_CSNT \ 223 | OR_GPCM_XACS \ 224 | OR_GPCM_SCY_15 \ 225 | OR_GPCM_TRLX_SET \ 226 | OR_GPCM_EHTR_SET \ 227 | OR_GPCM_EAD) 228 /* 0xfe0009f7 */ 229 230 /* 231 * Serial Port 232 */ 233 #define CONFIG_SYS_NS16550_SERIAL 234 #define CONFIG_SYS_NS16550_REG_SIZE 1 235 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 236 237 #define CONFIG_SYS_BAUDRATE_TABLE \ 238 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 239 240 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 241 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 242 243 #if defined(CONFIG_PCI) 244 /* 245 * General PCI 246 * Addresses are mapped 1-1. 247 */ 248 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 249 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 250 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 251 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 252 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 253 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 254 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 255 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 256 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 257 258 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 259 #endif 260 261 /* 262 * TSEC 263 */ 264 265 #define CONFIG_TSEC1 266 #ifdef CONFIG_TSEC1 267 #define CONFIG_HAS_ETH0 268 #define CONFIG_TSEC1_NAME "TSEC1" 269 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 270 #define TSEC1_PHY_ADDR 0x01 271 #define TSEC1_FLAGS 0 272 #define TSEC1_PHYIDX 0 273 #endif 274 275 /* Options are: TSEC[0-1] */ 276 #define CONFIG_ETHPRIME "TSEC1" 277 278 /* 279 * Environment 280 */ 281 #define CONFIG_ENV_ADDR \ 282 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 283 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 284 #define CONFIG_ENV_SIZE 0x4000 285 /* Address and size of Redundant Environment Sector */ 286 #define CONFIG_ENV_OFFSET_REDUND \ 287 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 288 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 289 290 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 291 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 292 293 /* 294 * BOOTP options 295 */ 296 #define CONFIG_BOOTP_BOOTFILESIZE 297 298 /* 299 * Command line configuration. 300 */ 301 302 /* 303 * Miscellaneous configurable options 304 */ 305 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 306 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 307 308 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ 309 310 /* 311 * For booting Linux, the board info and command line data 312 * have to be in the first 256 MB of memory, since this is 313 * the maximum mapped by the Linux kernel during initialization. 314 */ 315 /* Initial Memory map for Linux*/ 316 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 317 318 /* 0x64050000 */ 319 #define CONFIG_SYS_HRCW_LOW (\ 320 0x20000000 /* reserved, must be set */ |\ 321 HRCWL_DDRCM |\ 322 HRCWL_CSB_TO_CLKIN_4X1 | \ 323 HRCWL_CORE_TO_CSB_2_5X1) 324 325 /* 0xa0600004 */ 326 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ 327 HRCWH_PCI_ARBITER_ENABLE | \ 328 HRCWH_CORE_ENABLE | \ 329 HRCWH_FROM_0X00000100 | \ 330 HRCWH_BOOTSEQ_DISABLE |\ 331 HRCWH_SW_WATCHDOG_DISABLE |\ 332 HRCWH_ROM_LOC_LOCAL_16BIT | \ 333 HRCWH_TSEC1M_IN_MII | \ 334 HRCWH_BIG_ENDIAN | \ 335 HRCWH_LALE_EARLY) 336 337 /* System IO Config */ 338 #define CONFIG_SYS_SICRH (0x01000000 | \ 339 SICRH_ETSEC2_B | \ 340 SICRH_ETSEC2_C | \ 341 SICRH_ETSEC2_D | \ 342 SICRH_ETSEC2_E | \ 343 SICRH_ETSEC2_F | \ 344 SICRH_ETSEC2_G | \ 345 SICRH_TSOBI1 | \ 346 SICRH_TSOBI2) 347 /* 0x010fff03 */ 348 #define CONFIG_SYS_SICRL (SICRL_LBC | \ 349 SICRL_SPI_A | \ 350 SICRL_SPI_B | \ 351 SICRL_SPI_C | \ 352 SICRL_SPI_D | \ 353 SICRL_ETSEC2_A) 354 /* 0x33fc0003) */ 355 356 #define CONFIG_SYS_HID0_INIT 0x000000000 357 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 358 HID0_ENABLE_INSTRUCTION_CACHE) 359 360 #define CONFIG_SYS_HID2 HID2_HBE 361 362 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 363 364 /* DDR @ 0x00000000 */ 365 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 366 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 367 | BATU_BL_256M \ 368 | BATU_VS \ 369 | BATU_VP) 370 371 #if defined(CONFIG_PCI) 372 /* PCI @ 0x80000000 */ 373 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 374 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 375 | BATU_BL_256M \ 376 | BATU_VS \ 377 | BATU_VP) 378 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 379 | BATL_PP_RW \ 380 | BATL_CACHEINHIBIT \ 381 | BATL_GUARDEDSTORAGE) 382 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 383 | BATU_BL_256M \ 384 | BATU_VS \ 385 | BATU_VP) 386 #else 387 #define CONFIG_SYS_IBAT1L (0) 388 #define CONFIG_SYS_IBAT1U (0) 389 #define CONFIG_SYS_IBAT2L (0) 390 #define CONFIG_SYS_IBAT2U (0) 391 #endif 392 393 /* PCI2 not supported on 8313 */ 394 #define CONFIG_SYS_IBAT3L (0) 395 #define CONFIG_SYS_IBAT3U (0) 396 #define CONFIG_SYS_IBAT4L (0) 397 #define CONFIG_SYS_IBAT4U (0) 398 399 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 400 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 401 | BATL_PP_RW \ 402 | BATL_CACHEINHIBIT \ 403 | BATL_GUARDEDSTORAGE) 404 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 405 | BATU_BL_256M \ 406 | BATU_VS \ 407 | BATU_VP) 408 409 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 410 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 411 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 412 413 /* FPGA, SRAM, NAND @ 0x60000000 */ 414 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 415 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) 416 417 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 418 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 419 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 420 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 421 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 422 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 423 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 424 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 425 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 426 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 427 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 428 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 429 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 430 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 431 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 432 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 433 434 #define CONFIG_NETDEV eth0 435 436 #define CONFIG_HOSTNAME "ve8313" 437 #define CONFIG_UBOOTPATH ve8313/u-boot.bin 438 439 #define CONFIG_EXTRA_ENV_SETTINGS \ 440 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 441 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ 442 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 443 "u-boot_addr_r=100000\0" \ 444 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 445 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ 446 " +${filesize};" \ 447 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 448 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ 449 " ${filesize};" \ 450 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ 451 452 #endif /* __CONFIG_H */ 453