1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * (C) Copyright 2010 5 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 /* 26 * ve8313 board configuration file 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_E300 1 36 #define CONFIG_MPC83xx 1 37 #define CONFIG_MPC831x 1 38 #define CONFIG_MPC8313 1 39 #define CONFIG_VE8313 1 40 41 #ifndef CONFIG_SYS_TEXT_BASE 42 #define CONFIG_SYS_TEXT_BASE 0xfe000000 43 #endif 44 45 #define CONFIG_PCI 1 46 #define CONFIG_FSL_ELBC 1 47 48 #define CONFIG_BOARD_EARLY_INIT_F 1 49 50 /* 51 * On-board devices 52 * 53 */ 54 #define CONFIG_83XX_CLKIN 32000000 /* in Hz */ 55 56 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 57 58 #define CONFIG_SYS_IMMR 0xE0000000 59 60 #define CONFIG_SYS_MEMTEST_START 0x00001000 61 #define CONFIG_SYS_MEMTEST_END 0x07000000 62 63 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ 64 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ 65 66 /* 67 * Device configurations 68 */ 69 70 /* 71 * DDR Setup 72 */ 73 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 75 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 76 77 /* 78 * Manually set up DDR parameters, as this board does not 79 * have the SPD connected to I2C. 80 */ 81 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 82 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 83 | CSCONFIG_AP \ 84 | CSCONFIG_ODT_RD_NEVER \ 85 | CSCONFIG_ODT_WR_ALL \ 86 | CSCONFIG_ROW_BIT_13 \ 87 | CSCONFIG_COL_BIT_10) 88 /* 0x80840102 */ 89 90 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 91 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 92 | (0 << TIMING_CFG0_WRT_SHIFT) \ 93 | (3 << TIMING_CFG0_RRT_SHIFT) \ 94 | (2 << TIMING_CFG0_WWT_SHIFT) \ 95 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 96 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 97 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 98 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 99 /* 0x0e720802 */ 100 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 101 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 102 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 103 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 104 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 105 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 106 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 107 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 108 /* 0x26256222 */ 109 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 110 | (5 << TIMING_CFG2_CPO_SHIFT) \ 111 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 112 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 113 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 114 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 115 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 116 /* 0x029028c7 */ 117 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ 118 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 119 /* 0x03202000 */ 120 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 121 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 122 | SDRAM_CFG_DBW_32) 123 /* 0x43080000 */ 124 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 125 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 126 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 127 /* 0x44400232 */ 128 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 129 130 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 131 /*0x02000000*/ 132 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 133 | DDRCDR_PZ_NOMZ \ 134 | DDRCDR_NZ_NOMZ \ 135 | DDRCDR_M_ODR) 136 /* 0x73000002 */ 137 138 /* 139 * FLASH on the Local Bus 140 */ 141 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 142 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 143 #define CONFIG_SYS_FLASH_BASE 0xFE000000 144 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ 145 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 146 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 147 148 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 149 | BR_PS_16 /* 16 bit */ \ 150 | BR_MS_GPCM /* MSEL = GPCM */ \ 151 | BR_V) /* valid */ 152 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 153 | OR_GPCM_CSNT \ 154 | OR_GPCM_ACS_DIV4 \ 155 | OR_GPCM_SCY_5 \ 156 | OR_GPCM_TRLX_SET \ 157 | OR_GPCM_EAD) 158 /* 0xfe000c55 */ 159 160 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 161 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 162 163 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 164 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ 165 166 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 167 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 168 169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 170 171 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 172 #define CONFIG_SYS_RAMBOOT 173 #endif 174 175 #define CONFIG_SYS_INIT_RAM_LOCK 1 176 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 177 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 178 179 #define CONFIG_SYS_GBL_DATA_OFFSET \ 180 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 181 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 182 183 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 184 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 185 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 186 187 /* 188 * Local Bus LCRR and LBCR regs 189 */ 190 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 191 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 192 193 #define CONFIG_SYS_LBC_LBCR 0x00040000 194 195 #define CONFIG_SYS_LBC_MRTPR 0x20000000 196 197 /* 198 * NAND settings 199 */ 200 #define CONFIG_SYS_NAND_BASE 0x61000000 201 #define CONFIG_SYS_MAX_NAND_DEVICE 1 202 #define CONFIG_MTD_NAND_VERIFY_WRITE 203 #define CONFIG_CMD_NAND 1 204 #define CONFIG_NAND_FSL_ELBC 1 205 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 206 207 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 208 | BR_PS_8 \ 209 | BR_DECC_CHK_GEN \ 210 | BR_MS_FCM \ 211 | BR_V) /* valid */ 212 /* 0x61000c21 */ 213 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 214 | OR_FCM_BCTLD \ 215 | OR_FCM_CHT \ 216 | OR_FCM_SCY_2 \ 217 | OR_FCM_RST \ 218 | OR_FCM_TRLX) 219 /* 0xffff90ac */ 220 221 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 222 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 223 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 224 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 225 226 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 227 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 228 229 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 230 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 231 232 /* CS2 NvRAM */ 233 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ 234 | BR_PS_8 \ 235 | BR_V) 236 /* 0x60000801 */ 237 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 238 | OR_GPCM_CSNT \ 239 | OR_GPCM_XACS \ 240 | OR_GPCM_SCY_3 \ 241 | OR_GPCM_TRLX_SET \ 242 | OR_GPCM_EHTR_SET \ 243 | OR_GPCM_EAD) 244 /* 0xfffe0937 */ 245 /* local bus read write buffer mapping SRAM@0x64000000 */ 246 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \ 247 | BR_PS_16 \ 248 | BR_V) 249 /* 0x62001001 */ 250 251 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \ 252 | OR_GPCM_CSNT \ 253 | OR_GPCM_XACS \ 254 | OR_GPCM_SCY_15 \ 255 | OR_GPCM_TRLX_SET \ 256 | OR_GPCM_EHTR_SET \ 257 | OR_GPCM_EAD) 258 /* 0xfe0009f7 */ 259 260 /* pass open firmware flat tree */ 261 #define CONFIG_OF_LIBFDT 1 262 #define CONFIG_OF_BOARD_SETUP 1 263 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 264 265 /* 266 * Serial Port 267 */ 268 #define CONFIG_CONS_INDEX 1 269 #define CONFIG_SYS_NS16550 270 #define CONFIG_SYS_NS16550_SERIAL 271 #define CONFIG_SYS_NS16550_REG_SIZE 1 272 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 273 274 #define CONFIG_SYS_BAUDRATE_TABLE \ 275 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 276 277 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 278 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 279 280 /* Use the HUSH parser */ 281 #define CONFIG_SYS_HUSH_PARSER 282 283 #if defined(CONFIG_PCI) 284 /* 285 * General PCI 286 * Addresses are mapped 1-1. 287 */ 288 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 289 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 290 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 291 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 292 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 293 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 294 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 295 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 296 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 297 298 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 299 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 300 #endif 301 302 /* 303 * TSEC 304 */ 305 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 306 307 308 #define CONFIG_TSEC1 309 #ifdef CONFIG_TSEC1 310 #define CONFIG_HAS_ETH0 311 #define CONFIG_TSEC1_NAME "TSEC1" 312 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 313 #define TSEC1_PHY_ADDR 0x01 314 #define TSEC1_FLAGS 0 315 #define TSEC1_PHYIDX 0 316 #endif 317 318 /* Options are: TSEC[0-1] */ 319 #define CONFIG_ETHPRIME "TSEC1" 320 321 /* 322 * Environment 323 */ 324 #define CONFIG_ENV_IS_IN_FLASH 1 325 #define CONFIG_ENV_ADDR \ 326 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 327 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 328 #define CONFIG_ENV_SIZE 0x4000 329 /* Address and size of Redundant Environment Sector */ 330 #define CONFIG_ENV_OFFSET_REDUND \ 331 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 332 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 333 334 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 335 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 336 337 /* 338 * BOOTP options 339 */ 340 #define CONFIG_BOOTP_BOOTFILESIZE 341 #define CONFIG_BOOTP_BOOTPATH 342 #define CONFIG_BOOTP_GATEWAY 343 #define CONFIG_BOOTP_HOSTNAME 344 345 /* 346 * Command line configuration. 347 */ 348 #include <config_cmd_default.h> 349 350 #define CONFIG_CMD_DHCP 351 #define CONFIG_CMD_MII 352 #define CONFIG_CMD_PING 353 #define CONFIG_CMD_PCI 354 355 #define CONFIG_CMDLINE_EDITING 1 356 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 357 358 /* 359 * Miscellaneous configurable options 360 */ 361 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 362 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 363 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 364 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 365 366 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 367 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 368 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ 369 #define CONFIG_SYS_HZ 1000 /* 1ms ticks */ 370 371 /* 372 * For booting Linux, the board info and command line data 373 * have to be in the first 256 MB of memory, since this is 374 * the maximum mapped by the Linux kernel during initialization. 375 */ 376 /* Initial Memory map for Linux*/ 377 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 378 379 /* 0x64050000 */ 380 #define CONFIG_SYS_HRCW_LOW (\ 381 0x20000000 /* reserved, must be set */ |\ 382 HRCWL_DDRCM |\ 383 HRCWL_CSB_TO_CLKIN_4X1 | \ 384 HRCWL_CORE_TO_CSB_2_5X1) 385 386 /* 0xa0600004 */ 387 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ 388 HRCWH_PCI_ARBITER_ENABLE | \ 389 HRCWH_CORE_ENABLE | \ 390 HRCWH_FROM_0X00000100 | \ 391 HRCWH_BOOTSEQ_DISABLE |\ 392 HRCWH_SW_WATCHDOG_DISABLE |\ 393 HRCWH_ROM_LOC_LOCAL_16BIT | \ 394 HRCWH_TSEC1M_IN_MII | \ 395 HRCWH_BIG_ENDIAN | \ 396 HRCWH_LALE_EARLY) 397 398 /* System IO Config */ 399 #define CONFIG_SYS_SICRH (0x01000000 | \ 400 SICRH_ETSEC2_B | \ 401 SICRH_ETSEC2_C | \ 402 SICRH_ETSEC2_D | \ 403 SICRH_ETSEC2_E | \ 404 SICRH_ETSEC2_F | \ 405 SICRH_ETSEC2_G | \ 406 SICRH_TSOBI1 | \ 407 SICRH_TSOBI2) 408 /* 0x010fff03 */ 409 #define CONFIG_SYS_SICRL (SICRL_LBC | \ 410 SICRL_SPI_A | \ 411 SICRL_SPI_B | \ 412 SICRL_SPI_C | \ 413 SICRL_SPI_D | \ 414 SICRL_ETSEC2_A) 415 /* 0x33fc0003) */ 416 417 #define CONFIG_SYS_HID0_INIT 0x000000000 418 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 419 HID0_ENABLE_INSTRUCTION_CACHE) 420 421 #define CONFIG_SYS_HID2 HID2_HBE 422 423 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 424 425 /* DDR @ 0x00000000 */ 426 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 427 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 428 | BATU_BL_256M \ 429 | BATU_VS \ 430 | BATU_VP) 431 432 #if defined(CONFIG_PCI) 433 /* PCI @ 0x80000000 */ 434 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 435 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 436 | BATU_BL_256M \ 437 | BATU_VS \ 438 | BATU_VP) 439 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 440 | BATL_PP_RW \ 441 | BATL_CACHEINHIBIT \ 442 | BATL_GUARDEDSTORAGE) 443 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 444 | BATU_BL_256M \ 445 | BATU_VS \ 446 | BATU_VP) 447 #else 448 #define CONFIG_SYS_IBAT1L (0) 449 #define CONFIG_SYS_IBAT1U (0) 450 #define CONFIG_SYS_IBAT2L (0) 451 #define CONFIG_SYS_IBAT2U (0) 452 #endif 453 454 /* PCI2 not supported on 8313 */ 455 #define CONFIG_SYS_IBAT3L (0) 456 #define CONFIG_SYS_IBAT3U (0) 457 #define CONFIG_SYS_IBAT4L (0) 458 #define CONFIG_SYS_IBAT4U (0) 459 460 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 461 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 462 | BATL_PP_RW \ 463 | BATL_CACHEINHIBIT \ 464 | BATL_GUARDEDSTORAGE) 465 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 466 | BATU_BL_256M \ 467 | BATU_VS \ 468 | BATU_VP) 469 470 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 471 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 472 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 473 474 /* FPGA, SRAM, NAND @ 0x60000000 */ 475 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 476 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) 477 478 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 479 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 480 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 481 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 482 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 483 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 484 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 485 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 486 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 487 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 488 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 489 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 490 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 491 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 492 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 493 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 494 495 #define CONFIG_NETDEV eth0 496 497 #define CONFIG_HOSTNAME ve8313 498 #define CONFIG_UBOOTPATH ve8313/u-boot.bin 499 500 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 501 #define CONFIG_BAUDRATE 115200 502 503 #define XMK_STR(x) #x 504 #define MK_STR(x) XMK_STR(x) 505 506 #define CONFIG_EXTRA_ENV_SETTINGS \ 507 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 508 "ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0" \ 509 "u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 510 "u-boot_addr_r=100000\0" \ 511 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 512 "update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 513 "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 514 "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \ 515 " ${filesize};" \ 516 "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ 517 518 #undef MK_STR 519 #undef XMK_STR 520 521 #endif /* __CONFIG_H */ 522