1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * (C) Copyright 2010 5 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 /* 10 * ve8313 board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_E300 1 20 #define CONFIG_MPC83xx 1 21 #define CONFIG_MPC831x 1 22 #define CONFIG_MPC8313 1 23 #define CONFIG_VE8313 1 24 25 #ifndef CONFIG_SYS_TEXT_BASE 26 #define CONFIG_SYS_TEXT_BASE 0xfe000000 27 #endif 28 29 #define CONFIG_PCI 1 30 #define CONFIG_PCI_INDIRECT_BRIDGE 1 31 #define CONFIG_FSL_ELBC 1 32 33 #define CONFIG_BOARD_EARLY_INIT_F 1 34 35 /* 36 * On-board devices 37 * 38 */ 39 #define CONFIG_83XX_CLKIN 32000000 /* in Hz */ 40 41 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 42 43 #define CONFIG_SYS_IMMR 0xE0000000 44 45 #define CONFIG_SYS_MEMTEST_START 0x00001000 46 #define CONFIG_SYS_MEMTEST_END 0x07000000 47 48 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ 49 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ 50 51 /* 52 * Device configurations 53 */ 54 55 /* 56 * DDR Setup 57 */ 58 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 59 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 60 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 61 62 /* 63 * Manually set up DDR parameters, as this board does not 64 * have the SPD connected to I2C. 65 */ 66 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 67 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 68 | CSCONFIG_AP \ 69 | CSCONFIG_ODT_RD_NEVER \ 70 | CSCONFIG_ODT_WR_ALL \ 71 | CSCONFIG_ROW_BIT_13 \ 72 | CSCONFIG_COL_BIT_10) 73 /* 0x80840102 */ 74 75 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 76 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 77 | (0 << TIMING_CFG0_WRT_SHIFT) \ 78 | (3 << TIMING_CFG0_RRT_SHIFT) \ 79 | (2 << TIMING_CFG0_WWT_SHIFT) \ 80 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 81 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 82 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 83 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 84 /* 0x0e720802 */ 85 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 86 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 87 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 88 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 89 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 90 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 91 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 92 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 93 /* 0x26256222 */ 94 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 95 | (5 << TIMING_CFG2_CPO_SHIFT) \ 96 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 97 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 98 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 99 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 100 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 101 /* 0x029028c7 */ 102 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ 103 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 104 /* 0x03202000 */ 105 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 106 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 107 | SDRAM_CFG_DBW_32) 108 /* 0x43080000 */ 109 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 110 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 111 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 112 /* 0x44400232 */ 113 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 114 115 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 116 /*0x02000000*/ 117 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 118 | DDRCDR_PZ_NOMZ \ 119 | DDRCDR_NZ_NOMZ \ 120 | DDRCDR_M_ODR) 121 /* 0x73000002 */ 122 123 /* 124 * FLASH on the Local Bus 125 */ 126 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 127 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 128 #define CONFIG_SYS_FLASH_BASE 0xFE000000 129 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ 130 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 131 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 132 133 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 134 | BR_PS_16 /* 16 bit */ \ 135 | BR_MS_GPCM /* MSEL = GPCM */ \ 136 | BR_V) /* valid */ 137 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 138 | OR_GPCM_CSNT \ 139 | OR_GPCM_ACS_DIV4 \ 140 | OR_GPCM_SCY_5 \ 141 | OR_GPCM_TRLX_SET \ 142 | OR_GPCM_EAD) 143 /* 0xfe000c55 */ 144 145 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 146 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 147 148 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 149 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ 150 151 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 152 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 153 154 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 155 156 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 157 #define CONFIG_SYS_RAMBOOT 158 #endif 159 160 #define CONFIG_SYS_INIT_RAM_LOCK 1 161 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 162 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 163 164 #define CONFIG_SYS_GBL_DATA_OFFSET \ 165 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 166 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 167 168 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 169 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 170 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 171 172 /* 173 * Local Bus LCRR and LBCR regs 174 */ 175 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 176 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 177 178 #define CONFIG_SYS_LBC_LBCR 0x00040000 179 180 #define CONFIG_SYS_LBC_MRTPR 0x20000000 181 182 /* 183 * NAND settings 184 */ 185 #define CONFIG_SYS_NAND_BASE 0x61000000 186 #define CONFIG_SYS_MAX_NAND_DEVICE 1 187 #define CONFIG_MTD_NAND_VERIFY_WRITE 188 #define CONFIG_CMD_NAND 1 189 #define CONFIG_NAND_FSL_ELBC 1 190 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 191 192 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 193 | BR_PS_8 \ 194 | BR_DECC_CHK_GEN \ 195 | BR_MS_FCM \ 196 | BR_V) /* valid */ 197 /* 0x61000c21 */ 198 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 199 | OR_FCM_BCTLD \ 200 | OR_FCM_CHT \ 201 | OR_FCM_SCY_2 \ 202 | OR_FCM_RST \ 203 | OR_FCM_TRLX) 204 /* 0xffff90ac */ 205 206 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 207 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 208 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 209 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 210 211 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 212 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 213 214 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 215 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 216 217 /* CS2 NvRAM */ 218 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ 219 | BR_PS_8 \ 220 | BR_V) 221 /* 0x60000801 */ 222 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 223 | OR_GPCM_CSNT \ 224 | OR_GPCM_XACS \ 225 | OR_GPCM_SCY_3 \ 226 | OR_GPCM_TRLX_SET \ 227 | OR_GPCM_EHTR_SET \ 228 | OR_GPCM_EAD) 229 /* 0xfffe0937 */ 230 /* local bus read write buffer mapping SRAM@0x64000000 */ 231 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \ 232 | BR_PS_16 \ 233 | BR_V) 234 /* 0x62001001 */ 235 236 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \ 237 | OR_GPCM_CSNT \ 238 | OR_GPCM_XACS \ 239 | OR_GPCM_SCY_15 \ 240 | OR_GPCM_TRLX_SET \ 241 | OR_GPCM_EHTR_SET \ 242 | OR_GPCM_EAD) 243 /* 0xfe0009f7 */ 244 245 /* pass open firmware flat tree */ 246 #define CONFIG_OF_LIBFDT 1 247 #define CONFIG_OF_BOARD_SETUP 1 248 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 249 250 /* 251 * Serial Port 252 */ 253 #define CONFIG_CONS_INDEX 1 254 #define CONFIG_SYS_NS16550 255 #define CONFIG_SYS_NS16550_SERIAL 256 #define CONFIG_SYS_NS16550_REG_SIZE 1 257 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 258 259 #define CONFIG_SYS_BAUDRATE_TABLE \ 260 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 261 262 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 263 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 264 265 /* Use the HUSH parser */ 266 #define CONFIG_SYS_HUSH_PARSER 267 268 #if defined(CONFIG_PCI) 269 /* 270 * General PCI 271 * Addresses are mapped 1-1. 272 */ 273 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 274 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 275 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 276 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 277 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 278 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 279 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 280 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 281 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 282 283 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 284 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 285 #endif 286 287 /* 288 * TSEC 289 */ 290 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 291 292 293 #define CONFIG_TSEC1 294 #ifdef CONFIG_TSEC1 295 #define CONFIG_HAS_ETH0 296 #define CONFIG_TSEC1_NAME "TSEC1" 297 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 298 #define TSEC1_PHY_ADDR 0x01 299 #define TSEC1_FLAGS 0 300 #define TSEC1_PHYIDX 0 301 #endif 302 303 /* Options are: TSEC[0-1] */ 304 #define CONFIG_ETHPRIME "TSEC1" 305 306 /* 307 * Environment 308 */ 309 #define CONFIG_ENV_IS_IN_FLASH 1 310 #define CONFIG_ENV_ADDR \ 311 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 312 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 313 #define CONFIG_ENV_SIZE 0x4000 314 /* Address and size of Redundant Environment Sector */ 315 #define CONFIG_ENV_OFFSET_REDUND \ 316 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 317 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 318 319 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 320 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 321 322 /* 323 * BOOTP options 324 */ 325 #define CONFIG_BOOTP_BOOTFILESIZE 326 #define CONFIG_BOOTP_BOOTPATH 327 #define CONFIG_BOOTP_GATEWAY 328 #define CONFIG_BOOTP_HOSTNAME 329 330 /* 331 * Command line configuration. 332 */ 333 #include <config_cmd_default.h> 334 335 #define CONFIG_CMD_DHCP 336 #define CONFIG_CMD_MII 337 #define CONFIG_CMD_PING 338 #define CONFIG_CMD_PCI 339 340 #define CONFIG_CMDLINE_EDITING 1 341 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 342 343 /* 344 * Miscellaneous configurable options 345 */ 346 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 347 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 348 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 349 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 350 351 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 352 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 353 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ 354 #define CONFIG_SYS_HZ 1000 /* 1ms ticks */ 355 356 /* 357 * For booting Linux, the board info and command line data 358 * have to be in the first 256 MB of memory, since this is 359 * the maximum mapped by the Linux kernel during initialization. 360 */ 361 /* Initial Memory map for Linux*/ 362 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 363 364 /* 0x64050000 */ 365 #define CONFIG_SYS_HRCW_LOW (\ 366 0x20000000 /* reserved, must be set */ |\ 367 HRCWL_DDRCM |\ 368 HRCWL_CSB_TO_CLKIN_4X1 | \ 369 HRCWL_CORE_TO_CSB_2_5X1) 370 371 /* 0xa0600004 */ 372 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ 373 HRCWH_PCI_ARBITER_ENABLE | \ 374 HRCWH_CORE_ENABLE | \ 375 HRCWH_FROM_0X00000100 | \ 376 HRCWH_BOOTSEQ_DISABLE |\ 377 HRCWH_SW_WATCHDOG_DISABLE |\ 378 HRCWH_ROM_LOC_LOCAL_16BIT | \ 379 HRCWH_TSEC1M_IN_MII | \ 380 HRCWH_BIG_ENDIAN | \ 381 HRCWH_LALE_EARLY) 382 383 /* System IO Config */ 384 #define CONFIG_SYS_SICRH (0x01000000 | \ 385 SICRH_ETSEC2_B | \ 386 SICRH_ETSEC2_C | \ 387 SICRH_ETSEC2_D | \ 388 SICRH_ETSEC2_E | \ 389 SICRH_ETSEC2_F | \ 390 SICRH_ETSEC2_G | \ 391 SICRH_TSOBI1 | \ 392 SICRH_TSOBI2) 393 /* 0x010fff03 */ 394 #define CONFIG_SYS_SICRL (SICRL_LBC | \ 395 SICRL_SPI_A | \ 396 SICRL_SPI_B | \ 397 SICRL_SPI_C | \ 398 SICRL_SPI_D | \ 399 SICRL_ETSEC2_A) 400 /* 0x33fc0003) */ 401 402 #define CONFIG_SYS_HID0_INIT 0x000000000 403 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 404 HID0_ENABLE_INSTRUCTION_CACHE) 405 406 #define CONFIG_SYS_HID2 HID2_HBE 407 408 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 409 410 /* DDR @ 0x00000000 */ 411 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 412 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 413 | BATU_BL_256M \ 414 | BATU_VS \ 415 | BATU_VP) 416 417 #if defined(CONFIG_PCI) 418 /* PCI @ 0x80000000 */ 419 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 420 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 421 | BATU_BL_256M \ 422 | BATU_VS \ 423 | BATU_VP) 424 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 425 | BATL_PP_RW \ 426 | BATL_CACHEINHIBIT \ 427 | BATL_GUARDEDSTORAGE) 428 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 429 | BATU_BL_256M \ 430 | BATU_VS \ 431 | BATU_VP) 432 #else 433 #define CONFIG_SYS_IBAT1L (0) 434 #define CONFIG_SYS_IBAT1U (0) 435 #define CONFIG_SYS_IBAT2L (0) 436 #define CONFIG_SYS_IBAT2U (0) 437 #endif 438 439 /* PCI2 not supported on 8313 */ 440 #define CONFIG_SYS_IBAT3L (0) 441 #define CONFIG_SYS_IBAT3U (0) 442 #define CONFIG_SYS_IBAT4L (0) 443 #define CONFIG_SYS_IBAT4U (0) 444 445 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 446 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 447 | BATL_PP_RW \ 448 | BATL_CACHEINHIBIT \ 449 | BATL_GUARDEDSTORAGE) 450 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 451 | BATU_BL_256M \ 452 | BATU_VS \ 453 | BATU_VP) 454 455 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 456 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 457 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 458 459 /* FPGA, SRAM, NAND @ 0x60000000 */ 460 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 461 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) 462 463 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 464 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 465 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 466 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 467 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 468 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 469 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 470 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 471 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 472 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 473 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 474 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 475 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 476 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 477 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 478 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 479 480 #define CONFIG_NETDEV eth0 481 482 #define CONFIG_HOSTNAME ve8313 483 #define CONFIG_UBOOTPATH ve8313/u-boot.bin 484 485 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 486 #define CONFIG_BAUDRATE 115200 487 488 #define CONFIG_EXTRA_ENV_SETTINGS \ 489 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 490 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ 491 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 492 "u-boot_addr_r=100000\0" \ 493 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 494 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ 495 " +${filesize};" \ 496 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 497 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ 498 " ${filesize};" \ 499 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ 500 501 #endif /* __CONFIG_H */ 502