1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * (C) Copyright 2010 5 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 /* 10 * ve8313 board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_E300 1 20 #define CONFIG_MPC831x 1 21 #define CONFIG_MPC8313 1 22 #define CONFIG_VE8313 1 23 24 #ifndef CONFIG_SYS_TEXT_BASE 25 #define CONFIG_SYS_TEXT_BASE 0xfe000000 26 #endif 27 28 #define CONFIG_PCI 1 29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 30 #define CONFIG_FSL_ELBC 1 31 32 #define CONFIG_BOARD_EARLY_INIT_F 1 33 34 /* 35 * On-board devices 36 * 37 */ 38 #define CONFIG_83XX_CLKIN 32000000 /* in Hz */ 39 40 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 41 42 #define CONFIG_SYS_IMMR 0xE0000000 43 44 #define CONFIG_SYS_MEMTEST_START 0x00001000 45 #define CONFIG_SYS_MEMTEST_END 0x07000000 46 47 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ 48 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ 49 50 /* 51 * Device configurations 52 */ 53 54 /* 55 * DDR Setup 56 */ 57 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 58 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 59 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 60 61 /* 62 * Manually set up DDR parameters, as this board does not 63 * have the SPD connected to I2C. 64 */ 65 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 66 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 67 | CSCONFIG_AP \ 68 | CSCONFIG_ODT_RD_NEVER \ 69 | CSCONFIG_ODT_WR_ALL \ 70 | CSCONFIG_ROW_BIT_13 \ 71 | CSCONFIG_COL_BIT_10) 72 /* 0x80840102 */ 73 74 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 75 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 76 | (0 << TIMING_CFG0_WRT_SHIFT) \ 77 | (3 << TIMING_CFG0_RRT_SHIFT) \ 78 | (2 << TIMING_CFG0_WWT_SHIFT) \ 79 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 80 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 81 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 82 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 83 /* 0x0e720802 */ 84 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 85 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 86 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 87 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 88 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 89 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 90 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 91 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 92 /* 0x26256222 */ 93 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 94 | (5 << TIMING_CFG2_CPO_SHIFT) \ 95 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 96 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 97 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 98 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 99 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 100 /* 0x029028c7 */ 101 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ 102 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 103 /* 0x03202000 */ 104 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 105 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 106 | SDRAM_CFG_DBW_32) 107 /* 0x43080000 */ 108 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 109 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 110 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 111 /* 0x44400232 */ 112 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 113 114 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 115 /*0x02000000*/ 116 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 117 | DDRCDR_PZ_NOMZ \ 118 | DDRCDR_NZ_NOMZ \ 119 | DDRCDR_M_ODR) 120 /* 0x73000002 */ 121 122 /* 123 * FLASH on the Local Bus 124 */ 125 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 126 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 127 #define CONFIG_SYS_FLASH_BASE 0xFE000000 128 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ 129 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 131 132 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 133 | BR_PS_16 /* 16 bit */ \ 134 | BR_MS_GPCM /* MSEL = GPCM */ \ 135 | BR_V) /* valid */ 136 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 137 | OR_GPCM_CSNT \ 138 | OR_GPCM_ACS_DIV4 \ 139 | OR_GPCM_SCY_5 \ 140 | OR_GPCM_TRLX_SET \ 141 | OR_GPCM_EAD) 142 /* 0xfe000c55 */ 143 144 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 145 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 146 147 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 148 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ 149 150 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 151 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 152 153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 154 155 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 156 #define CONFIG_SYS_RAMBOOT 157 #endif 158 159 #define CONFIG_SYS_INIT_RAM_LOCK 1 160 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 161 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 162 163 #define CONFIG_SYS_GBL_DATA_OFFSET \ 164 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 165 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 166 167 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 168 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 169 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 170 171 /* 172 * Local Bus LCRR and LBCR regs 173 */ 174 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 175 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 176 177 #define CONFIG_SYS_LBC_LBCR 0x00040000 178 179 #define CONFIG_SYS_LBC_MRTPR 0x20000000 180 181 /* 182 * NAND settings 183 */ 184 #define CONFIG_SYS_NAND_BASE 0x61000000 185 #define CONFIG_SYS_MAX_NAND_DEVICE 1 186 #define CONFIG_CMD_NAND 1 187 #define CONFIG_NAND_FSL_ELBC 1 188 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 189 190 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 191 | BR_PS_8 \ 192 | BR_DECC_CHK_GEN \ 193 | BR_MS_FCM \ 194 | BR_V) /* valid */ 195 /* 0x61000c21 */ 196 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 197 | OR_FCM_BCTLD \ 198 | OR_FCM_CHT \ 199 | OR_FCM_SCY_2 \ 200 | OR_FCM_RST \ 201 | OR_FCM_TRLX) 202 /* 0xffff90ac */ 203 204 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 205 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 206 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 207 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 208 209 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 210 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 211 212 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 213 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 214 215 /* CS2 NvRAM */ 216 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ 217 | BR_PS_8 \ 218 | BR_V) 219 /* 0x60000801 */ 220 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 221 | OR_GPCM_CSNT \ 222 | OR_GPCM_XACS \ 223 | OR_GPCM_SCY_3 \ 224 | OR_GPCM_TRLX_SET \ 225 | OR_GPCM_EHTR_SET \ 226 | OR_GPCM_EAD) 227 /* 0xfffe0937 */ 228 /* local bus read write buffer mapping SRAM@0x64000000 */ 229 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \ 230 | BR_PS_16 \ 231 | BR_V) 232 /* 0x62001001 */ 233 234 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \ 235 | OR_GPCM_CSNT \ 236 | OR_GPCM_XACS \ 237 | OR_GPCM_SCY_15 \ 238 | OR_GPCM_TRLX_SET \ 239 | OR_GPCM_EHTR_SET \ 240 | OR_GPCM_EAD) 241 /* 0xfe0009f7 */ 242 243 /* 244 * Serial Port 245 */ 246 #define CONFIG_CONS_INDEX 1 247 #define CONFIG_SYS_NS16550_SERIAL 248 #define CONFIG_SYS_NS16550_REG_SIZE 1 249 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 250 251 #define CONFIG_SYS_BAUDRATE_TABLE \ 252 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 253 254 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 255 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 256 257 #if defined(CONFIG_PCI) 258 /* 259 * General PCI 260 * Addresses are mapped 1-1. 261 */ 262 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 263 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 264 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 265 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 266 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 267 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 268 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 269 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 270 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 271 272 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 273 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 274 #endif 275 276 /* 277 * TSEC 278 */ 279 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 280 281 #define CONFIG_TSEC1 282 #ifdef CONFIG_TSEC1 283 #define CONFIG_HAS_ETH0 284 #define CONFIG_TSEC1_NAME "TSEC1" 285 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 286 #define TSEC1_PHY_ADDR 0x01 287 #define TSEC1_FLAGS 0 288 #define TSEC1_PHYIDX 0 289 #endif 290 291 /* Options are: TSEC[0-1] */ 292 #define CONFIG_ETHPRIME "TSEC1" 293 294 /* 295 * Environment 296 */ 297 #define CONFIG_ENV_IS_IN_FLASH 1 298 #define CONFIG_ENV_ADDR \ 299 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 300 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 301 #define CONFIG_ENV_SIZE 0x4000 302 /* Address and size of Redundant Environment Sector */ 303 #define CONFIG_ENV_OFFSET_REDUND \ 304 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 305 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 306 307 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 308 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 309 310 /* 311 * BOOTP options 312 */ 313 #define CONFIG_BOOTP_BOOTFILESIZE 314 #define CONFIG_BOOTP_BOOTPATH 315 #define CONFIG_BOOTP_GATEWAY 316 #define CONFIG_BOOTP_HOSTNAME 317 318 /* 319 * Command line configuration. 320 */ 321 #define CONFIG_CMD_PCI 322 323 #define CONFIG_CMDLINE_EDITING 1 324 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 325 326 /* 327 * Miscellaneous configurable options 328 */ 329 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 330 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 331 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 332 333 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 334 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 335 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ 336 337 /* 338 * For booting Linux, the board info and command line data 339 * have to be in the first 256 MB of memory, since this is 340 * the maximum mapped by the Linux kernel during initialization. 341 */ 342 /* Initial Memory map for Linux*/ 343 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 344 345 /* 0x64050000 */ 346 #define CONFIG_SYS_HRCW_LOW (\ 347 0x20000000 /* reserved, must be set */ |\ 348 HRCWL_DDRCM |\ 349 HRCWL_CSB_TO_CLKIN_4X1 | \ 350 HRCWL_CORE_TO_CSB_2_5X1) 351 352 /* 0xa0600004 */ 353 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ 354 HRCWH_PCI_ARBITER_ENABLE | \ 355 HRCWH_CORE_ENABLE | \ 356 HRCWH_FROM_0X00000100 | \ 357 HRCWH_BOOTSEQ_DISABLE |\ 358 HRCWH_SW_WATCHDOG_DISABLE |\ 359 HRCWH_ROM_LOC_LOCAL_16BIT | \ 360 HRCWH_TSEC1M_IN_MII | \ 361 HRCWH_BIG_ENDIAN | \ 362 HRCWH_LALE_EARLY) 363 364 /* System IO Config */ 365 #define CONFIG_SYS_SICRH (0x01000000 | \ 366 SICRH_ETSEC2_B | \ 367 SICRH_ETSEC2_C | \ 368 SICRH_ETSEC2_D | \ 369 SICRH_ETSEC2_E | \ 370 SICRH_ETSEC2_F | \ 371 SICRH_ETSEC2_G | \ 372 SICRH_TSOBI1 | \ 373 SICRH_TSOBI2) 374 /* 0x010fff03 */ 375 #define CONFIG_SYS_SICRL (SICRL_LBC | \ 376 SICRL_SPI_A | \ 377 SICRL_SPI_B | \ 378 SICRL_SPI_C | \ 379 SICRL_SPI_D | \ 380 SICRL_ETSEC2_A) 381 /* 0x33fc0003) */ 382 383 #define CONFIG_SYS_HID0_INIT 0x000000000 384 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 385 HID0_ENABLE_INSTRUCTION_CACHE) 386 387 #define CONFIG_SYS_HID2 HID2_HBE 388 389 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 390 391 /* DDR @ 0x00000000 */ 392 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 393 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 394 | BATU_BL_256M \ 395 | BATU_VS \ 396 | BATU_VP) 397 398 #if defined(CONFIG_PCI) 399 /* PCI @ 0x80000000 */ 400 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 401 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 402 | BATU_BL_256M \ 403 | BATU_VS \ 404 | BATU_VP) 405 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 406 | BATL_PP_RW \ 407 | BATL_CACHEINHIBIT \ 408 | BATL_GUARDEDSTORAGE) 409 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 410 | BATU_BL_256M \ 411 | BATU_VS \ 412 | BATU_VP) 413 #else 414 #define CONFIG_SYS_IBAT1L (0) 415 #define CONFIG_SYS_IBAT1U (0) 416 #define CONFIG_SYS_IBAT2L (0) 417 #define CONFIG_SYS_IBAT2U (0) 418 #endif 419 420 /* PCI2 not supported on 8313 */ 421 #define CONFIG_SYS_IBAT3L (0) 422 #define CONFIG_SYS_IBAT3U (0) 423 #define CONFIG_SYS_IBAT4L (0) 424 #define CONFIG_SYS_IBAT4U (0) 425 426 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 427 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 428 | BATL_PP_RW \ 429 | BATL_CACHEINHIBIT \ 430 | BATL_GUARDEDSTORAGE) 431 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 432 | BATU_BL_256M \ 433 | BATU_VS \ 434 | BATU_VP) 435 436 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 437 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 438 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 439 440 /* FPGA, SRAM, NAND @ 0x60000000 */ 441 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 442 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) 443 444 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 445 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 446 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 447 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 448 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 449 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 450 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 451 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 452 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 453 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 454 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 455 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 456 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 457 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 458 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 459 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 460 461 #define CONFIG_NETDEV eth0 462 463 #define CONFIG_HOSTNAME ve8313 464 #define CONFIG_UBOOTPATH ve8313/u-boot.bin 465 466 #define CONFIG_BAUDRATE 115200 467 468 #define CONFIG_EXTRA_ENV_SETTINGS \ 469 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 470 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ 471 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 472 "u-boot_addr_r=100000\0" \ 473 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 474 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ 475 " +${filesize};" \ 476 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 477 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ 478 " ${filesize};" \ 479 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ 480 481 #endif /* __CONFIG_H */ 482