1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * (C) Copyright 2010 5 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 /* 26 * ve8313 board configuration file 27 */ 28 29 #ifndef __CONFIG_H 30 #define __CONFIG_H 31 32 /* 33 * High Level Configuration Options 34 */ 35 #define CONFIG_E300 1 36 #define CONFIG_MPC83xx 1 37 #define CONFIG_MPC831x 1 38 #define CONFIG_MPC8313 1 39 #define CONFIG_VE8313 1 40 41 #ifndef CONFIG_SYS_TEXT_BASE 42 #define CONFIG_SYS_TEXT_BASE 0xfe000000 43 #endif 44 45 #define CONFIG_PCI 1 46 #define CONFIG_FSL_ELBC 1 47 48 #define CONFIG_BOARD_EARLY_INIT_F 1 49 50 /* 51 * On-board devices 52 * 53 */ 54 #define CONFIG_83XX_CLKIN 32000000 /* in Hz */ 55 56 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 57 58 #define CONFIG_SYS_IMMR 0xE0000000 59 60 #define CONFIG_SYS_MEMTEST_START 0x00001000 61 #define CONFIG_SYS_MEMTEST_END 0x07000000 62 63 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ 64 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ 65 66 /* 67 * Device configurations 68 */ 69 70 /* 71 * DDR Setup 72 */ 73 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 75 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 76 77 /* 78 * Manually set up DDR parameters, as this board does not 79 * have the SPD connected to I2C. 80 */ 81 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 82 #define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \ 83 | CSCONFIG_AP \ 84 | 0x00040000 /* TODO */ \ 85 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) 86 /* 0x80840102 */ 87 88 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 89 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ 90 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ 91 | ( 3 << TIMING_CFG0_RRT_SHIFT ) \ 92 | ( 2 << TIMING_CFG0_WWT_SHIFT ) \ 93 | ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ 94 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ 95 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ 96 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) 97 /* 0x0e720802 */ 98 #define CONFIG_SYS_DDR_TIMING_1 ( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \ 99 | ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ 100 | ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \ 101 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ 102 | ( 6 << TIMING_CFG1_REFREC_SHIFT ) \ 103 | ( 2 << TIMING_CFG1_WRREC_SHIFT ) \ 104 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ 105 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) 106 /* 0x26256222 */ 107 #define CONFIG_SYS_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ 108 | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ 109 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ 110 | ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ 111 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ 112 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ 113 | ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) ) 114 /* 0x029028c7 */ 115 #define CONFIG_SYS_DDR_INTERVAL ( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \ 116 | ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) 117 /* 0x03202000 */ 118 #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ 119 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 120 | SDRAM_CFG_32_BE ) 121 /* 0x43080000 */ 122 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 123 #define CONFIG_SYS_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ 124 | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) 125 /* 0x44400232 */ 126 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 127 128 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 129 /*0x02000000*/ 130 #define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \ 131 | DDRCDR_PZ_NOMZ \ 132 | DDRCDR_NZ_NOMZ \ 133 | DDRCDR_M_ODR ) 134 /* 0x73000002 */ 135 136 /* 137 * FLASH on the Local Bus 138 */ 139 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 140 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 141 #define CONFIG_SYS_FLASH_BASE 0xFE000000 142 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ 143 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 145 146 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | \ 147 (2 << BR_PS_SHIFT) | /* 16 bit */ \ 148 BR_V) /* valid */ 149 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 150 | OR_GPCM_CSNT \ 151 | OR_GPCM_ACS_DIV4 \ 152 | OR_GPCM_SCY_5 \ 153 | OR_GPCM_TRLX \ 154 | OR_GPCM_EAD) 155 /* 0xfe000c55 */ 156 157 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 158 #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ 159 160 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 161 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ 162 163 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 164 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 165 166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 167 168 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 169 #define CONFIG_SYS_RAMBOOT 170 #endif 171 172 #define CONFIG_SYS_INIT_RAM_LOCK 1 173 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 174 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ 175 176 #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ 177 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ 178 CONFIG_SYS_GBL_DATA_SIZE) 179 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 180 181 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 182 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 183 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 184 185 /* 186 * Local Bus LCRR and LBCR regs 187 */ 188 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 189 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 190 191 #define CONFIG_SYS_LBC_LBCR 0x00040000 192 193 #define CONFIG_SYS_LBC_MRTPR 0x20000000 194 195 /* 196 * NAND settings 197 */ 198 #define CONFIG_SYS_NAND_BASE 0x61000000 199 #define CONFIG_SYS_MAX_NAND_DEVICE 1 200 #define CONFIG_MTD_NAND_VERIFY_WRITE 201 #define CONFIG_CMD_NAND 1 202 #define CONFIG_NAND_FSL_ELBC 1 203 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 204 205 #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ 206 | BR_PS_8 \ 207 | BR_DECC_CHK_GEN \ 208 | BR_MS_FCM \ 209 | BR_V ) /* valid */ 210 /* 0x61000c21 */ 211 #define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \ 212 | OR_FCM_BCTLD \ 213 | OR_FCM_CHT \ 214 | OR_FCM_SCY_2 \ 215 | OR_FCM_RST \ 216 | OR_FCM_TRLX) 217 /* 0xffff90ac */ 218 219 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 220 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 221 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 222 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 223 224 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 225 #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ 226 227 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 228 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 229 230 /* CS2 NvRAM */ 231 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ 232 | BR_PS_8 \ 233 | BR_V) 234 /* 0x60000801 */ 235 #define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \ 236 | OR_GPCM_CSNT \ 237 | OR_GPCM_XACS \ 238 | OR_GPCM_SCY_3 \ 239 | OR_GPCM_TRLX \ 240 | OR_GPCM_EHTR \ 241 | OR_GPCM_EAD) 242 /* 0xfffe0937 */ 243 /* local bus read write buffer mapping SRAM@0x64000000 */ 244 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \ 245 | BR_PS_16 \ 246 | BR_V) 247 /* 0x62001001 */ 248 249 #define CONFIG_SYS_OR3_PRELIM (0xfe000000 \ 250 | OR_GPCM_CSNT \ 251 | OR_GPCM_XACS \ 252 | OR_GPCM_SCY_15 \ 253 | OR_GPCM_TRLX \ 254 | OR_GPCM_EHTR \ 255 | OR_GPCM_EAD) 256 /* 0xfe0009f7 */ 257 258 /* pass open firmware flat tree */ 259 #define CONFIG_OF_LIBFDT 1 260 #define CONFIG_OF_BOARD_SETUP 1 261 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 262 263 /* 264 * Serial Port 265 */ 266 #define CONFIG_CONS_INDEX 1 267 #define CONFIG_SYS_NS16550 268 #define CONFIG_SYS_NS16550_SERIAL 269 #define CONFIG_SYS_NS16550_REG_SIZE 1 270 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 271 272 #define CONFIG_SYS_BAUDRATE_TABLE \ 273 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 274 275 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 276 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 277 278 /* Use the HUSH parser */ 279 #define CONFIG_SYS_HUSH_PARSER 280 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 281 282 #if defined(CONFIG_PCI) 283 /* 284 * General PCI 285 * Addresses are mapped 1-1. 286 */ 287 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 288 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 289 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 290 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 291 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 292 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 293 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 294 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 295 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 296 297 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 298 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 299 #endif 300 301 /* 302 * TSEC 303 */ 304 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 305 306 #define CONFIG_NET_MULTI 307 308 #define CONFIG_TSEC1 309 #ifdef CONFIG_TSEC1 310 #define CONFIG_HAS_ETH0 311 #define CONFIG_TSEC1_NAME "TSEC1" 312 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 313 #define TSEC1_PHY_ADDR 0x01 314 #define TSEC1_FLAGS 0 315 #define TSEC1_PHYIDX 0 316 #endif 317 318 /* Options are: TSEC[0-1] */ 319 #define CONFIG_ETHPRIME "TSEC1" 320 321 /* 322 * Environment 323 */ 324 #define CONFIG_ENV_IS_IN_FLASH 1 325 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ 326 CONFIG_SYS_MONITOR_LEN) 327 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 328 #define CONFIG_ENV_SIZE 0x4000 329 /* Address and size of Redundant Environment Sector */ 330 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 331 CONFIG_ENV_SECT_SIZE) 332 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 333 334 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 335 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 336 337 /* 338 * BOOTP options 339 */ 340 #define CONFIG_BOOTP_BOOTFILESIZE 341 #define CONFIG_BOOTP_BOOTPATH 342 #define CONFIG_BOOTP_GATEWAY 343 #define CONFIG_BOOTP_HOSTNAME 344 345 /* 346 * Command line configuration. 347 */ 348 #include <config_cmd_default.h> 349 350 #define CONFIG_CMD_DHCP 351 #define CONFIG_CMD_MII 352 #define CONFIG_CMD_PING 353 #define CONFIG_CMD_PCI 354 355 #define CONFIG_CMDLINE_EDITING 1 356 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 357 358 /* 359 * Miscellaneous configurable options 360 */ 361 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 362 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 363 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 364 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 365 366 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 367 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 368 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ 369 #define CONFIG_SYS_HZ 1000 /* 1ms ticks */ 370 371 /* 372 * For booting Linux, the board info and command line data 373 * have to be in the first 256 MB of memory, since this is 374 * the maximum mapped by the Linux kernel during initialization. 375 */ 376 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ 377 378 /* 0x64050000 */ 379 #define CONFIG_SYS_HRCW_LOW (\ 380 0x20000000 /* reserved, must be set */ |\ 381 HRCWL_DDRCM |\ 382 HRCWL_CSB_TO_CLKIN_4X1 | \ 383 HRCWL_CORE_TO_CSB_2_5X1) 384 385 /* 0xa0600004 */ 386 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ 387 HRCWH_PCI_ARBITER_ENABLE | \ 388 HRCWH_CORE_ENABLE | \ 389 HRCWH_FROM_0X00000100 | \ 390 HRCWH_BOOTSEQ_DISABLE |\ 391 HRCWH_SW_WATCHDOG_DISABLE |\ 392 HRCWH_ROM_LOC_LOCAL_16BIT | \ 393 HRCWH_TSEC1M_IN_MII | \ 394 HRCWH_BIG_ENDIAN | \ 395 HRCWH_LALE_EARLY) 396 397 /* System IO Config */ 398 #define CONFIG_SYS_SICRH (0x01000000 | \ 399 SICRH_ETSEC2_B | \ 400 SICRH_ETSEC2_C | \ 401 SICRH_ETSEC2_D | \ 402 SICRH_ETSEC2_E | \ 403 SICRH_ETSEC2_F | \ 404 SICRH_ETSEC2_G | \ 405 SICRH_TSOBI1 | \ 406 SICRH_TSOBI2) 407 /* 0x010fff03 */ 408 #define CONFIG_SYS_SICRL (SICRL_LBC | \ 409 SICRL_SPI_A | \ 410 SICRL_SPI_B | \ 411 SICRL_SPI_C | \ 412 SICRL_SPI_D | \ 413 SICRL_ETSEC2_A) 414 /* 0x33fc0003) */ 415 416 #define CONFIG_SYS_HID0_INIT 0x000000000 417 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 418 HID0_ENABLE_INSTRUCTION_CACHE) 419 420 #define CONFIG_SYS_HID2 HID2_HBE 421 422 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 423 424 /* DDR @ 0x00000000 */ 425 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) 426 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ 427 BATU_VS | BATU_VP) 428 429 #if defined(CONFIG_PCI) 430 /* PCI @ 0x80000000 */ 431 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) 432 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ 433 BATU_VS | BATU_VP) 434 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \ 435 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 436 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ 437 BATU_VS | BATU_VP) 438 #else 439 #define CONFIG_SYS_IBAT1L (0) 440 #define CONFIG_SYS_IBAT1U (0) 441 #define CONFIG_SYS_IBAT2L (0) 442 #define CONFIG_SYS_IBAT2U (0) 443 #endif 444 445 /* PCI2 not supported on 8313 */ 446 #define CONFIG_SYS_IBAT3L (0) 447 #define CONFIG_SYS_IBAT3U (0) 448 #define CONFIG_SYS_IBAT4L (0) 449 #define CONFIG_SYS_IBAT4U (0) 450 451 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 452 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \ 453 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 454 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \ 455 BATU_VP) 456 457 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 458 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) 459 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 460 461 /* FPGA, SRAM, NAND @ 0x60000000 */ 462 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) 463 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) 464 465 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 466 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 467 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 468 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 469 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 470 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 471 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 472 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 473 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 474 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 475 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 476 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 477 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 478 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 479 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 480 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 481 482 #define CONFIG_NETDEV eth0 483 484 #define CONFIG_HOSTNAME ve8313 485 #define CONFIG_UBOOTPATH ve8313/u-boot.bin 486 487 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ 488 #define CONFIG_BAUDRATE 115200 489 490 #define XMK_STR(x) #x 491 #define MK_STR(x) XMK_STR(x) 492 493 #define CONFIG_EXTRA_ENV_SETTINGS \ 494 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ 495 "ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0" \ 496 "u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 497 "u-boot_addr_r=100000\0" \ 498 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 499 "update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 500 "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 501 "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \ 502 " ${filesize};" \ 503 "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ 504 505 #undef MK_STR 506 #undef XMK_STR 507 508 #endif /* __CONFIG_H */ 509