1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * (C) Copyright 2010 5 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 /* 10 * ve8313 board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_E300 1 20 #define CONFIG_MPC831x 1 21 #define CONFIG_MPC8313 1 22 23 #ifndef CONFIG_SYS_TEXT_BASE 24 #define CONFIG_SYS_TEXT_BASE 0xfe000000 25 #endif 26 27 #define CONFIG_PCI_INDIRECT_BRIDGE 1 28 #define CONFIG_FSL_ELBC 1 29 30 /* 31 * On-board devices 32 * 33 */ 34 #define CONFIG_83XX_CLKIN 32000000 /* in Hz */ 35 36 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 37 38 #define CONFIG_SYS_IMMR 0xE0000000 39 40 #define CONFIG_SYS_MEMTEST_START 0x00001000 41 #define CONFIG_SYS_MEMTEST_END 0x07000000 42 43 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ 44 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ 45 46 /* 47 * Device configurations 48 */ 49 50 /* 51 * DDR Setup 52 */ 53 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 54 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 55 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 56 57 /* 58 * Manually set up DDR parameters, as this board does not 59 * have the SPD connected to I2C. 60 */ 61 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 62 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 63 | CSCONFIG_AP \ 64 | CSCONFIG_ODT_RD_NEVER \ 65 | CSCONFIG_ODT_WR_ALL \ 66 | CSCONFIG_ROW_BIT_13 \ 67 | CSCONFIG_COL_BIT_10) 68 /* 0x80840102 */ 69 70 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 71 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 72 | (0 << TIMING_CFG0_WRT_SHIFT) \ 73 | (3 << TIMING_CFG0_RRT_SHIFT) \ 74 | (2 << TIMING_CFG0_WWT_SHIFT) \ 75 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 76 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 77 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 78 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 79 /* 0x0e720802 */ 80 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 81 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 82 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 83 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 84 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 85 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 86 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 87 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 88 /* 0x26256222 */ 89 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 90 | (5 << TIMING_CFG2_CPO_SHIFT) \ 91 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 92 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 93 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 94 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 95 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 96 /* 0x029028c7 */ 97 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ 98 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 99 /* 0x03202000 */ 100 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 101 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 102 | SDRAM_CFG_DBW_32) 103 /* 0x43080000 */ 104 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 105 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 106 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 107 /* 0x44400232 */ 108 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 109 110 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 111 /*0x02000000*/ 112 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 113 | DDRCDR_PZ_NOMZ \ 114 | DDRCDR_NZ_NOMZ \ 115 | DDRCDR_M_ODR) 116 /* 0x73000002 */ 117 118 /* 119 * FLASH on the Local Bus 120 */ 121 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 122 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 123 #define CONFIG_SYS_FLASH_BASE 0xFE000000 124 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ 125 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 126 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 127 128 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 129 | BR_PS_16 /* 16 bit */ \ 130 | BR_MS_GPCM /* MSEL = GPCM */ \ 131 | BR_V) /* valid */ 132 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 133 | OR_GPCM_CSNT \ 134 | OR_GPCM_ACS_DIV4 \ 135 | OR_GPCM_SCY_5 \ 136 | OR_GPCM_TRLX_SET \ 137 | OR_GPCM_EAD) 138 /* 0xfe000c55 */ 139 140 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 141 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 142 143 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 144 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ 145 146 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 147 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 148 149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 150 151 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 152 #define CONFIG_SYS_RAMBOOT 153 #endif 154 155 #define CONFIG_SYS_INIT_RAM_LOCK 1 156 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 157 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 158 159 #define CONFIG_SYS_GBL_DATA_OFFSET \ 160 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 161 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 162 163 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 164 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 165 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 166 167 /* 168 * Local Bus LCRR and LBCR regs 169 */ 170 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 171 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 172 173 #define CONFIG_SYS_LBC_LBCR 0x00040000 174 175 #define CONFIG_SYS_LBC_MRTPR 0x20000000 176 177 /* 178 * NAND settings 179 */ 180 #define CONFIG_SYS_NAND_BASE 0x61000000 181 #define CONFIG_SYS_MAX_NAND_DEVICE 1 182 #define CONFIG_NAND_FSL_ELBC 1 183 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 184 185 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 186 | BR_PS_8 \ 187 | BR_DECC_CHK_GEN \ 188 | BR_MS_FCM \ 189 | BR_V) /* valid */ 190 /* 0x61000c21 */ 191 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 192 | OR_FCM_BCTLD \ 193 | OR_FCM_CHT \ 194 | OR_FCM_SCY_2 \ 195 | OR_FCM_RST \ 196 | OR_FCM_TRLX) 197 /* 0xffff90ac */ 198 199 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 200 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 201 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 202 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 203 204 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 205 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 206 207 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 208 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 209 210 /* CS2 NvRAM */ 211 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ 212 | BR_PS_8 \ 213 | BR_V) 214 /* 0x60000801 */ 215 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 216 | OR_GPCM_CSNT \ 217 | OR_GPCM_XACS \ 218 | OR_GPCM_SCY_3 \ 219 | OR_GPCM_TRLX_SET \ 220 | OR_GPCM_EHTR_SET \ 221 | OR_GPCM_EAD) 222 /* 0xfffe0937 */ 223 /* local bus read write buffer mapping SRAM@0x64000000 */ 224 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \ 225 | BR_PS_16 \ 226 | BR_V) 227 /* 0x62001001 */ 228 229 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \ 230 | OR_GPCM_CSNT \ 231 | OR_GPCM_XACS \ 232 | OR_GPCM_SCY_15 \ 233 | OR_GPCM_TRLX_SET \ 234 | OR_GPCM_EHTR_SET \ 235 | OR_GPCM_EAD) 236 /* 0xfe0009f7 */ 237 238 /* 239 * Serial Port 240 */ 241 #define CONFIG_CONS_INDEX 1 242 #define CONFIG_SYS_NS16550_SERIAL 243 #define CONFIG_SYS_NS16550_REG_SIZE 1 244 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 245 246 #define CONFIG_SYS_BAUDRATE_TABLE \ 247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 248 249 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 250 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 251 252 #if defined(CONFIG_PCI) 253 /* 254 * General PCI 255 * Addresses are mapped 1-1. 256 */ 257 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 258 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 259 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 260 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 261 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 262 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 263 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 264 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 265 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 266 267 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 268 #endif 269 270 /* 271 * TSEC 272 */ 273 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 274 275 #define CONFIG_TSEC1 276 #ifdef CONFIG_TSEC1 277 #define CONFIG_HAS_ETH0 278 #define CONFIG_TSEC1_NAME "TSEC1" 279 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 280 #define TSEC1_PHY_ADDR 0x01 281 #define TSEC1_FLAGS 0 282 #define TSEC1_PHYIDX 0 283 #endif 284 285 /* Options are: TSEC[0-1] */ 286 #define CONFIG_ETHPRIME "TSEC1" 287 288 /* 289 * Environment 290 */ 291 #define CONFIG_ENV_ADDR \ 292 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 293 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 294 #define CONFIG_ENV_SIZE 0x4000 295 /* Address and size of Redundant Environment Sector */ 296 #define CONFIG_ENV_OFFSET_REDUND \ 297 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 298 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 299 300 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 301 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 302 303 /* 304 * BOOTP options 305 */ 306 #define CONFIG_BOOTP_BOOTFILESIZE 307 #define CONFIG_BOOTP_BOOTPATH 308 #define CONFIG_BOOTP_GATEWAY 309 #define CONFIG_BOOTP_HOSTNAME 310 311 /* 312 * Command line configuration. 313 */ 314 315 #define CONFIG_CMDLINE_EDITING 1 316 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 317 318 /* 319 * Miscellaneous configurable options 320 */ 321 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 322 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 323 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 324 325 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ 326 327 /* 328 * For booting Linux, the board info and command line data 329 * have to be in the first 256 MB of memory, since this is 330 * the maximum mapped by the Linux kernel during initialization. 331 */ 332 /* Initial Memory map for Linux*/ 333 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 334 335 /* 0x64050000 */ 336 #define CONFIG_SYS_HRCW_LOW (\ 337 0x20000000 /* reserved, must be set */ |\ 338 HRCWL_DDRCM |\ 339 HRCWL_CSB_TO_CLKIN_4X1 | \ 340 HRCWL_CORE_TO_CSB_2_5X1) 341 342 /* 0xa0600004 */ 343 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ 344 HRCWH_PCI_ARBITER_ENABLE | \ 345 HRCWH_CORE_ENABLE | \ 346 HRCWH_FROM_0X00000100 | \ 347 HRCWH_BOOTSEQ_DISABLE |\ 348 HRCWH_SW_WATCHDOG_DISABLE |\ 349 HRCWH_ROM_LOC_LOCAL_16BIT | \ 350 HRCWH_TSEC1M_IN_MII | \ 351 HRCWH_BIG_ENDIAN | \ 352 HRCWH_LALE_EARLY) 353 354 /* System IO Config */ 355 #define CONFIG_SYS_SICRH (0x01000000 | \ 356 SICRH_ETSEC2_B | \ 357 SICRH_ETSEC2_C | \ 358 SICRH_ETSEC2_D | \ 359 SICRH_ETSEC2_E | \ 360 SICRH_ETSEC2_F | \ 361 SICRH_ETSEC2_G | \ 362 SICRH_TSOBI1 | \ 363 SICRH_TSOBI2) 364 /* 0x010fff03 */ 365 #define CONFIG_SYS_SICRL (SICRL_LBC | \ 366 SICRL_SPI_A | \ 367 SICRL_SPI_B | \ 368 SICRL_SPI_C | \ 369 SICRL_SPI_D | \ 370 SICRL_ETSEC2_A) 371 /* 0x33fc0003) */ 372 373 #define CONFIG_SYS_HID0_INIT 0x000000000 374 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 375 HID0_ENABLE_INSTRUCTION_CACHE) 376 377 #define CONFIG_SYS_HID2 HID2_HBE 378 379 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 380 381 /* DDR @ 0x00000000 */ 382 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 383 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 384 | BATU_BL_256M \ 385 | BATU_VS \ 386 | BATU_VP) 387 388 #if defined(CONFIG_PCI) 389 /* PCI @ 0x80000000 */ 390 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 391 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 392 | BATU_BL_256M \ 393 | BATU_VS \ 394 | BATU_VP) 395 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 396 | BATL_PP_RW \ 397 | BATL_CACHEINHIBIT \ 398 | BATL_GUARDEDSTORAGE) 399 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 400 | BATU_BL_256M \ 401 | BATU_VS \ 402 | BATU_VP) 403 #else 404 #define CONFIG_SYS_IBAT1L (0) 405 #define CONFIG_SYS_IBAT1U (0) 406 #define CONFIG_SYS_IBAT2L (0) 407 #define CONFIG_SYS_IBAT2U (0) 408 #endif 409 410 /* PCI2 not supported on 8313 */ 411 #define CONFIG_SYS_IBAT3L (0) 412 #define CONFIG_SYS_IBAT3U (0) 413 #define CONFIG_SYS_IBAT4L (0) 414 #define CONFIG_SYS_IBAT4U (0) 415 416 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 417 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 418 | BATL_PP_RW \ 419 | BATL_CACHEINHIBIT \ 420 | BATL_GUARDEDSTORAGE) 421 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 422 | BATU_BL_256M \ 423 | BATU_VS \ 424 | BATU_VP) 425 426 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 427 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 428 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 429 430 /* FPGA, SRAM, NAND @ 0x60000000 */ 431 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 432 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) 433 434 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 435 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 436 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 437 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 438 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 439 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 440 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 441 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 442 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 443 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 444 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 445 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 446 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 447 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 448 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 449 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 450 451 #define CONFIG_NETDEV eth0 452 453 #define CONFIG_HOSTNAME ve8313 454 #define CONFIG_UBOOTPATH ve8313/u-boot.bin 455 456 #define CONFIG_EXTRA_ENV_SETTINGS \ 457 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 458 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ 459 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 460 "u-boot_addr_r=100000\0" \ 461 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 462 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ 463 " +${filesize};" \ 464 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 465 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ 466 " ${filesize};" \ 467 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ 468 469 #endif /* __CONFIG_H */ 470