1 /* 2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 3 * 4 * (C) Copyright 2010 5 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 /* 10 * ve8313 board configuration file 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_E300 1 20 #define CONFIG_MPC831x 1 21 #define CONFIG_MPC8313 1 22 #define CONFIG_VE8313 1 23 24 #ifndef CONFIG_SYS_TEXT_BASE 25 #define CONFIG_SYS_TEXT_BASE 0xfe000000 26 #endif 27 28 #define CONFIG_PCI_INDIRECT_BRIDGE 1 29 #define CONFIG_FSL_ELBC 1 30 31 /* 32 * On-board devices 33 * 34 */ 35 #define CONFIG_83XX_CLKIN 32000000 /* in Hz */ 36 37 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN 38 39 #define CONFIG_SYS_IMMR 0xE0000000 40 41 #define CONFIG_SYS_MEMTEST_START 0x00001000 42 #define CONFIG_SYS_MEMTEST_END 0x07000000 43 44 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth */ 45 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count */ 46 47 /* 48 * Device configurations 49 */ 50 51 /* 52 * DDR Setup 53 */ 54 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ 55 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE 56 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE 57 58 /* 59 * Manually set up DDR parameters, as this board does not 60 * have the SPD connected to I2C. 61 */ 62 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 63 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 64 | CSCONFIG_AP \ 65 | CSCONFIG_ODT_RD_NEVER \ 66 | CSCONFIG_ODT_WR_ALL \ 67 | CSCONFIG_ROW_BIT_13 \ 68 | CSCONFIG_COL_BIT_10) 69 /* 0x80840102 */ 70 71 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 72 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 73 | (0 << TIMING_CFG0_WRT_SHIFT) \ 74 | (3 << TIMING_CFG0_RRT_SHIFT) \ 75 | (2 << TIMING_CFG0_WWT_SHIFT) \ 76 | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 77 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 78 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 79 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 80 /* 0x0e720802 */ 81 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 82 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 83 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 84 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 85 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 86 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 87 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 88 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 89 /* 0x26256222 */ 90 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 91 | (5 << TIMING_CFG2_CPO_SHIFT) \ 92 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 93 | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 94 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 95 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 96 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) 97 /* 0x029028c7 */ 98 #define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ 99 | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 100 /* 0x03202000 */ 101 #define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ 102 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 103 | SDRAM_CFG_DBW_32) 104 /* 0x43080000 */ 105 #define CONFIG_SYS_SDRAM_CFG2 0x00401000 106 #define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ 107 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 108 /* 0x44400232 */ 109 #define CONFIG_SYS_DDR_MODE_2 0x8000C000 110 111 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 112 /*0x02000000*/ 113 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 114 | DDRCDR_PZ_NOMZ \ 115 | DDRCDR_NZ_NOMZ \ 116 | DDRCDR_M_ODR) 117 /* 0x73000002 */ 118 119 /* 120 * FLASH on the Local Bus 121 */ 122 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ 123 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ 124 #define CONFIG_SYS_FLASH_BASE 0xFE000000 125 #define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ 126 #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ 127 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ 128 129 #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ 130 | BR_PS_16 /* 16 bit */ \ 131 | BR_MS_GPCM /* MSEL = GPCM */ \ 132 | BR_V) /* valid */ 133 #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ 134 | OR_GPCM_CSNT \ 135 | OR_GPCM_ACS_DIV4 \ 136 | OR_GPCM_SCY_5 \ 137 | OR_GPCM_TRLX_SET \ 138 | OR_GPCM_EAD) 139 /* 0xfe000c55 */ 140 141 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE 142 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) 143 144 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 145 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ 146 147 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 148 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 149 150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 151 152 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 153 #define CONFIG_SYS_RAMBOOT 154 #endif 155 156 #define CONFIG_SYS_INIT_RAM_LOCK 1 157 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ 158 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ 159 160 #define CONFIG_SYS_GBL_DATA_OFFSET \ 161 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 162 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 163 164 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ 165 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 166 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) 167 168 /* 169 * Local Bus LCRR and LBCR regs 170 */ 171 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_3 172 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 173 174 #define CONFIG_SYS_LBC_LBCR 0x00040000 175 176 #define CONFIG_SYS_LBC_MRTPR 0x20000000 177 178 /* 179 * NAND settings 180 */ 181 #define CONFIG_SYS_NAND_BASE 0x61000000 182 #define CONFIG_SYS_MAX_NAND_DEVICE 1 183 #define CONFIG_NAND_FSL_ELBC 1 184 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 185 186 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ 187 | BR_PS_8 \ 188 | BR_DECC_CHK_GEN \ 189 | BR_MS_FCM \ 190 | BR_V) /* valid */ 191 /* 0x61000c21 */ 192 #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ 193 | OR_FCM_BCTLD \ 194 | OR_FCM_CHT \ 195 | OR_FCM_SCY_2 \ 196 | OR_FCM_RST \ 197 | OR_FCM_TRLX) 198 /* 0xffff90ac */ 199 200 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM 201 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM 202 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM 203 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM 204 205 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE 206 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) 207 208 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM 209 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM 210 211 /* CS2 NvRAM */ 212 #define CONFIG_SYS_BR2_PRELIM (0x60000000 \ 213 | BR_PS_8 \ 214 | BR_V) 215 /* 0x60000801 */ 216 #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ 217 | OR_GPCM_CSNT \ 218 | OR_GPCM_XACS \ 219 | OR_GPCM_SCY_3 \ 220 | OR_GPCM_TRLX_SET \ 221 | OR_GPCM_EHTR_SET \ 222 | OR_GPCM_EAD) 223 /* 0xfffe0937 */ 224 /* local bus read write buffer mapping SRAM@0x64000000 */ 225 #define CONFIG_SYS_BR3_PRELIM (0x62000000 \ 226 | BR_PS_16 \ 227 | BR_V) 228 /* 0x62001001 */ 229 230 #define CONFIG_SYS_OR3_PRELIM (OR_AM_32MB \ 231 | OR_GPCM_CSNT \ 232 | OR_GPCM_XACS \ 233 | OR_GPCM_SCY_15 \ 234 | OR_GPCM_TRLX_SET \ 235 | OR_GPCM_EHTR_SET \ 236 | OR_GPCM_EAD) 237 /* 0xfe0009f7 */ 238 239 /* 240 * Serial Port 241 */ 242 #define CONFIG_CONS_INDEX 1 243 #define CONFIG_SYS_NS16550_SERIAL 244 #define CONFIG_SYS_NS16550_REG_SIZE 1 245 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 246 247 #define CONFIG_SYS_BAUDRATE_TABLE \ 248 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 249 250 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) 251 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) 252 253 #if defined(CONFIG_PCI) 254 /* 255 * General PCI 256 * Addresses are mapped 1-1. 257 */ 258 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 259 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 260 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 261 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 262 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 263 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 264 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 265 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 266 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 267 268 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 269 #endif 270 271 /* 272 * TSEC 273 */ 274 #define CONFIG_TSEC_ENET /* TSEC ethernet support */ 275 276 #define CONFIG_TSEC1 277 #ifdef CONFIG_TSEC1 278 #define CONFIG_HAS_ETH0 279 #define CONFIG_TSEC1_NAME "TSEC1" 280 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 281 #define TSEC1_PHY_ADDR 0x01 282 #define TSEC1_FLAGS 0 283 #define TSEC1_PHYIDX 0 284 #endif 285 286 /* Options are: TSEC[0-1] */ 287 #define CONFIG_ETHPRIME "TSEC1" 288 289 /* 290 * Environment 291 */ 292 #define CONFIG_ENV_ADDR \ 293 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 294 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 295 #define CONFIG_ENV_SIZE 0x4000 296 /* Address and size of Redundant Environment Sector */ 297 #define CONFIG_ENV_OFFSET_REDUND \ 298 (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 299 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 300 301 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 302 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 303 304 /* 305 * BOOTP options 306 */ 307 #define CONFIG_BOOTP_BOOTFILESIZE 308 #define CONFIG_BOOTP_BOOTPATH 309 #define CONFIG_BOOTP_GATEWAY 310 #define CONFIG_BOOTP_HOSTNAME 311 312 /* 313 * Command line configuration. 314 */ 315 316 #define CONFIG_CMDLINE_EDITING 1 317 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 318 319 /* 320 * Miscellaneous configurable options 321 */ 322 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 323 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 324 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 325 326 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 327 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 328 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ 329 330 /* 331 * For booting Linux, the board info and command line data 332 * have to be in the first 256 MB of memory, since this is 333 * the maximum mapped by the Linux kernel during initialization. 334 */ 335 /* Initial Memory map for Linux*/ 336 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 337 338 /* 0x64050000 */ 339 #define CONFIG_SYS_HRCW_LOW (\ 340 0x20000000 /* reserved, must be set */ |\ 341 HRCWL_DDRCM |\ 342 HRCWL_CSB_TO_CLKIN_4X1 | \ 343 HRCWL_CORE_TO_CSB_2_5X1) 344 345 /* 0xa0600004 */ 346 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ 347 HRCWH_PCI_ARBITER_ENABLE | \ 348 HRCWH_CORE_ENABLE | \ 349 HRCWH_FROM_0X00000100 | \ 350 HRCWH_BOOTSEQ_DISABLE |\ 351 HRCWH_SW_WATCHDOG_DISABLE |\ 352 HRCWH_ROM_LOC_LOCAL_16BIT | \ 353 HRCWH_TSEC1M_IN_MII | \ 354 HRCWH_BIG_ENDIAN | \ 355 HRCWH_LALE_EARLY) 356 357 /* System IO Config */ 358 #define CONFIG_SYS_SICRH (0x01000000 | \ 359 SICRH_ETSEC2_B | \ 360 SICRH_ETSEC2_C | \ 361 SICRH_ETSEC2_D | \ 362 SICRH_ETSEC2_E | \ 363 SICRH_ETSEC2_F | \ 364 SICRH_ETSEC2_G | \ 365 SICRH_TSOBI1 | \ 366 SICRH_TSOBI2) 367 /* 0x010fff03 */ 368 #define CONFIG_SYS_SICRL (SICRL_LBC | \ 369 SICRL_SPI_A | \ 370 SICRL_SPI_B | \ 371 SICRL_SPI_C | \ 372 SICRL_SPI_D | \ 373 SICRL_ETSEC2_A) 374 /* 0x33fc0003) */ 375 376 #define CONFIG_SYS_HID0_INIT 0x000000000 377 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ 378 HID0_ENABLE_INSTRUCTION_CACHE) 379 380 #define CONFIG_SYS_HID2 HID2_HBE 381 382 #define CONFIG_HIGH_BATS 1 /* High BATs supported */ 383 384 /* DDR @ 0x00000000 */ 385 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) 386 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ 387 | BATU_BL_256M \ 388 | BATU_VS \ 389 | BATU_VP) 390 391 #if defined(CONFIG_PCI) 392 /* PCI @ 0x80000000 */ 393 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) 394 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ 395 | BATU_BL_256M \ 396 | BATU_VS \ 397 | BATU_VP) 398 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ 399 | BATL_PP_RW \ 400 | BATL_CACHEINHIBIT \ 401 | BATL_GUARDEDSTORAGE) 402 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ 403 | BATU_BL_256M \ 404 | BATU_VS \ 405 | BATU_VP) 406 #else 407 #define CONFIG_SYS_IBAT1L (0) 408 #define CONFIG_SYS_IBAT1U (0) 409 #define CONFIG_SYS_IBAT2L (0) 410 #define CONFIG_SYS_IBAT2U (0) 411 #endif 412 413 /* PCI2 not supported on 8313 */ 414 #define CONFIG_SYS_IBAT3L (0) 415 #define CONFIG_SYS_IBAT3U (0) 416 #define CONFIG_SYS_IBAT4L (0) 417 #define CONFIG_SYS_IBAT4U (0) 418 419 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ 420 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ 421 | BATL_PP_RW \ 422 | BATL_CACHEINHIBIT \ 423 | BATL_GUARDEDSTORAGE) 424 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ 425 | BATU_BL_256M \ 426 | BATU_VS \ 427 | BATU_VP) 428 429 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ 430 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 431 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 432 433 /* FPGA, SRAM, NAND @ 0x60000000 */ 434 #define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) 435 #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) 436 437 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 438 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 439 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 440 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 441 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 442 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 443 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 444 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 445 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L 446 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 447 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L 448 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 449 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 450 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 451 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 452 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 453 454 #define CONFIG_NETDEV eth0 455 456 #define CONFIG_HOSTNAME ve8313 457 #define CONFIG_UBOOTPATH ve8313/u-boot.bin 458 459 #define CONFIG_EXTRA_ENV_SETTINGS \ 460 "netdev=" __stringify(CONFIG_NETDEV) "\0" \ 461 "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ 462 "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 463 "u-boot_addr_r=100000\0" \ 464 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 465 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ 466 " +${filesize};" \ 467 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ 468 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ 469 " ${filesize};" \ 470 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ 471 472 #endif /* __CONFIG_H */ 473