xref: /openbmc/u-boot/include/configs/ve8313.h (revision 1494cc89)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) Freescale Semiconductor, Inc. 2006.
4  *
5  * (C) Copyright 2010
6  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7  */
8 /*
9  * ve8313 board configuration file
10  */
11 
12 #ifndef __CONFIG_H
13 #define __CONFIG_H
14 
15 /*
16  * High Level Configuration Options
17  */
18 #define CONFIG_E300		1
19 #define CONFIG_MPC831x		1
20 #define CONFIG_MPC8313		1
21 
22 #define CONFIG_PCI_INDIRECT_BRIDGE 1
23 #define CONFIG_FSL_ELBC		1
24 
25 /*
26  * On-board devices
27  *
28  */
29 #define CONFIG_83XX_CLKIN	32000000	/* in Hz */
30 
31 #define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
32 
33 #define CONFIG_SYS_IMMR		0xE0000000
34 
35 #define CONFIG_SYS_MEMTEST_START	0x00001000
36 #define CONFIG_SYS_MEMTEST_END		0x07000000
37 
38 #define CONFIG_SYS_ACR_PIPE_DEP		3	/* Arbiter pipeline depth */
39 #define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count */
40 
41 /*
42  * Device configurations
43  */
44 
45 /*
46  * DDR Setup
47  */
48 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory*/
49 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
50 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
51 
52 /*
53  * Manually set up DDR parameters, as this board does not
54  * have the SPD connected to I2C.
55  */
56 #define CONFIG_SYS_DDR_SIZE	128	/* MB */
57 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
58 				| CSCONFIG_AP \
59 				| CSCONFIG_ODT_RD_NEVER \
60 				| CSCONFIG_ODT_WR_ALL \
61 				| CSCONFIG_ROW_BIT_13 \
62 				| CSCONFIG_COL_BIT_10)
63 				/* 0x80840102 */
64 
65 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
66 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
67 				| (0 << TIMING_CFG0_WRT_SHIFT) \
68 				| (3 << TIMING_CFG0_RRT_SHIFT) \
69 				| (2 << TIMING_CFG0_WWT_SHIFT) \
70 				| (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
71 				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
72 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
73 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
74 				/* 0x0e720802 */
75 #define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
76 				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
77 				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
78 				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
79 				| (6 << TIMING_CFG1_REFREC_SHIFT) \
80 				| (2 << TIMING_CFG1_WRREC_SHIFT) \
81 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
82 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
83 				/* 0x26256222 */
84 #define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
85 				| (5 << TIMING_CFG2_CPO_SHIFT) \
86 				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
87 				| (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
88 				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
89 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
90 				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
91 				/* 0x029028c7 */
92 #define CONFIG_SYS_DDR_INTERVAL	((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \
93 				| (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
94 				/* 0x03202000 */
95 #define CONFIG_SYS_SDRAM_CFG	(SDRAM_CFG_SREN \
96 				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
97 				| SDRAM_CFG_DBW_32)
98 				/* 0x43080000 */
99 #define CONFIG_SYS_SDRAM_CFG2	0x00401000
100 #define CONFIG_SYS_DDR_MODE	((0x4440 << SDRAM_MODE_ESD_SHIFT) \
101 				| (0x0232 << SDRAM_MODE_SD_SHIFT))
102 				/* 0x44400232 */
103 #define CONFIG_SYS_DDR_MODE_2	0x8000C000
104 
105 #define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
106 				/*0x02000000*/
107 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
108 				| DDRCDR_PZ_NOMZ \
109 				| DDRCDR_NZ_NOMZ \
110 				| DDRCDR_M_ODR)
111 				/* 0x73000002 */
112 
113 /*
114  * FLASH on the Local Bus
115  */
116 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
117 #define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
118 #define CONFIG_SYS_FLASH_BASE		0xFE000000
119 #define CONFIG_SYS_FLASH_SIZE		32	/* size in MB */
120 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
121 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
122 
123 #define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE \
124 					| BR_PS_16	/* 16 bit */ \
125 					| BR_MS_GPCM	/* MSEL = GPCM */ \
126 					| BR_V)		/* valid */
127 #define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
128 					| OR_GPCM_CSNT \
129 					| OR_GPCM_ACS_DIV4 \
130 					| OR_GPCM_SCY_5 \
131 					| OR_GPCM_TRLX_SET \
132 					| OR_GPCM_EAD)
133 					/* 0xfe000c55 */
134 
135 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
136 #define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)
137 
138 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
139 #define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per dev */
140 
141 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
142 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
143 
144 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
145 
146 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
147 #define CONFIG_SYS_RAMBOOT
148 #endif
149 
150 #define CONFIG_SYS_INIT_RAM_LOCK	1
151 #define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
152 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM*/
153 
154 #define CONFIG_SYS_GBL_DATA_OFFSET	\
155 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
156 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
157 
158 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
159 #define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
160 #define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
161 
162 /*
163  * Local Bus LCRR and LBCR regs
164  */
165 #define CONFIG_SYS_LCRR_EADC	LCRR_EADC_3
166 #define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2
167 
168 #define CONFIG_SYS_LBC_LBCR	0x00040000
169 
170 #define CONFIG_SYS_LBC_MRTPR	0x20000000
171 
172 /*
173  * NAND settings
174  */
175 #define CONFIG_SYS_NAND_BASE		0x61000000
176 #define CONFIG_SYS_MAX_NAND_DEVICE	1
177 #define CONFIG_NAND_FSL_ELBC 1
178 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384
179 
180 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE \
181 					| BR_PS_8		\
182 					| BR_DECC_CHK_GEN	\
183 					| BR_MS_FCM		\
184 					| BR_V)	/* valid */
185 					/* 0x61000c21 */
186 #define CONFIG_SYS_NAND_OR_PRELIM	(OR_AM_32KB \
187 					| OR_FCM_BCTLD \
188 					| OR_FCM_CHT \
189 					| OR_FCM_SCY_2 \
190 					| OR_FCM_RST \
191 					| OR_FCM_TRLX)
192 					/* 0xffff90ac */
193 
194 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
195 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
196 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
197 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
198 
199 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
200 #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)
201 
202 #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
203 #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
204 
205 /* CS2 NvRAM */
206 #define CONFIG_SYS_BR2_PRELIM	(0x60000000 \
207 				| BR_PS_8 \
208 				| BR_V)
209 				/* 0x60000801 */
210 #define CONFIG_SYS_OR2_PRELIM	(OR_AM_128KB \
211 				| OR_GPCM_CSNT \
212 				| OR_GPCM_XACS \
213 				| OR_GPCM_SCY_3 \
214 				| OR_GPCM_TRLX_SET \
215 				| OR_GPCM_EHTR_SET \
216 				| OR_GPCM_EAD)
217 				/* 0xfffe0937 */
218 /* local bus read write buffer mapping SRAM@0x64000000 */
219 #define CONFIG_SYS_BR3_PRELIM	(0x62000000 \
220 				| BR_PS_16 \
221 				| BR_V)
222 				/* 0x62001001 */
223 
224 #define CONFIG_SYS_OR3_PRELIM	(OR_AM_32MB \
225 				| OR_GPCM_CSNT \
226 				| OR_GPCM_XACS \
227 				| OR_GPCM_SCY_15 \
228 				| OR_GPCM_TRLX_SET \
229 				| OR_GPCM_EHTR_SET \
230 				| OR_GPCM_EAD)
231 				/* 0xfe0009f7 */
232 
233 /*
234  * Serial Port
235  */
236 #define CONFIG_SYS_NS16550_SERIAL
237 #define CONFIG_SYS_NS16550_REG_SIZE	1
238 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
239 
240 #define CONFIG_SYS_BAUDRATE_TABLE	\
241 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
242 
243 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
244 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
245 
246 #if defined(CONFIG_PCI)
247 /*
248  * General PCI
249  * Addresses are mapped 1-1.
250  */
251 #define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
252 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
253 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
254 #define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
255 #define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
256 #define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
257 #define CONFIG_SYS_PCI1_IO_BASE		0x00000000
258 #define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
259 #define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */
260 
261 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
262 #endif
263 
264 /*
265  * TSEC
266  */
267 
268 #define CONFIG_TSEC1
269 #ifdef CONFIG_TSEC1
270 #define CONFIG_HAS_ETH0
271 #define CONFIG_TSEC1_NAME	"TSEC1"
272 #define CONFIG_SYS_TSEC1_OFFSET	0x24000
273 #define TSEC1_PHY_ADDR		0x01
274 #define TSEC1_FLAGS		0
275 #define TSEC1_PHYIDX		0
276 #endif
277 
278 /* Options are: TSEC[0-1] */
279 #define CONFIG_ETHPRIME			"TSEC1"
280 
281 /*
282  * Environment
283  */
284 #define CONFIG_ENV_ADDR		\
285 			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
286 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
287 #define CONFIG_ENV_SIZE		0x4000
288 /* Address and size of Redundant Environment Sector */
289 #define CONFIG_ENV_OFFSET_REDUND	\
290 			(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
291 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
292 
293 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
294 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
295 
296 /*
297  * BOOTP options
298  */
299 #define CONFIG_BOOTP_BOOTFILESIZE
300 
301 /*
302  * Command line configuration.
303  */
304 
305 /*
306  * Miscellaneous configurable options
307  */
308 #define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
309 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
310 
311 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
312 
313 /*
314  * For booting Linux, the board info and command line data
315  * have to be in the first 256 MB of memory, since this is
316  * the maximum mapped by the Linux kernel during initialization.
317  */
318 				/* Initial Memory map for Linux*/
319 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)
320 
321 /* 0x64050000 */
322 #define CONFIG_SYS_HRCW_LOW (\
323 	0x20000000 /* reserved, must be set */ |\
324 	HRCWL_DDRCM |\
325 	HRCWL_CSB_TO_CLKIN_4X1 | \
326 	HRCWL_CORE_TO_CSB_2_5X1)
327 
328 /* 0xa0600004 */
329 #define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
330 	HRCWH_PCI_ARBITER_ENABLE | \
331 	HRCWH_CORE_ENABLE | \
332 	HRCWH_FROM_0X00000100 | \
333 	HRCWH_BOOTSEQ_DISABLE |\
334 	HRCWH_SW_WATCHDOG_DISABLE |\
335 	HRCWH_ROM_LOC_LOCAL_16BIT | \
336 	HRCWH_TSEC1M_IN_MII | \
337 	HRCWH_BIG_ENDIAN | \
338 	HRCWH_LALE_EARLY)
339 
340 /* System IO Config */
341 #define CONFIG_SYS_SICRH	(0x01000000 | \
342 				SICRH_ETSEC2_B | \
343 				SICRH_ETSEC2_C | \
344 				SICRH_ETSEC2_D | \
345 				SICRH_ETSEC2_E | \
346 				SICRH_ETSEC2_F | \
347 				SICRH_ETSEC2_G | \
348 				SICRH_TSOBI1 | \
349 				SICRH_TSOBI2)
350 				/* 0x010fff03 */
351 #define CONFIG_SYS_SICRL	(SICRL_LBC | \
352 				SICRL_SPI_A | \
353 				SICRL_SPI_B | \
354 				SICRL_SPI_C | \
355 				SICRL_SPI_D | \
356 				SICRL_ETSEC2_A)
357 				/* 0x33fc0003) */
358 
359 #define CONFIG_SYS_HID0_INIT	0x000000000
360 #define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
361 				 HID0_ENABLE_INSTRUCTION_CACHE)
362 
363 #define CONFIG_SYS_HID2 HID2_HBE
364 
365 #define CONFIG_HIGH_BATS	1	/* High BATs supported */
366 
367 /* DDR @ 0x00000000 */
368 #define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
369 #define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
370 				| BATU_BL_256M \
371 				| BATU_VS \
372 				| BATU_VP)
373 
374 #if defined(CONFIG_PCI)
375 /* PCI @ 0x80000000 */
376 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
377 #define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE \
378 				| BATU_BL_256M \
379 				| BATU_VS \
380 				| BATU_VP)
381 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE \
382 				| BATL_PP_RW \
383 				| BATL_CACHEINHIBIT \
384 				| BATL_GUARDEDSTORAGE)
385 #define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE \
386 				| BATU_BL_256M \
387 				| BATU_VS \
388 				| BATU_VP)
389 #else
390 #define CONFIG_SYS_IBAT1L	(0)
391 #define CONFIG_SYS_IBAT1U	(0)
392 #define CONFIG_SYS_IBAT2L	(0)
393 #define CONFIG_SYS_IBAT2U	(0)
394 #endif
395 
396 /* PCI2 not supported on 8313 */
397 #define CONFIG_SYS_IBAT3L	(0)
398 #define CONFIG_SYS_IBAT3U	(0)
399 #define CONFIG_SYS_IBAT4L	(0)
400 #define CONFIG_SYS_IBAT4U	(0)
401 
402 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
403 #define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR \
404 				| BATL_PP_RW \
405 				| BATL_CACHEINHIBIT \
406 				| BATL_GUARDEDSTORAGE)
407 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR \
408 				| BATU_BL_256M \
409 				| BATU_VS \
410 				| BATU_VP)
411 
412 /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
413 #define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
414 #define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
415 
416 /*  FPGA, SRAM, NAND @ 0x60000000 */
417 #define CONFIG_SYS_IBAT7L	(0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE)
418 #define CONFIG_SYS_IBAT7U	(0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
419 
420 #define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
421 #define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
422 #define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
423 #define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
424 #define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
425 #define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
426 #define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
427 #define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
428 #define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
429 #define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
430 #define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
431 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
432 #define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
433 #define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
434 #define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
435 #define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
436 
437 #define CONFIG_NETDEV		eth0
438 
439 #define CONFIG_HOSTNAME		"ve8313"
440 #define CONFIG_UBOOTPATH	ve8313/u-boot.bin
441 
442 #define CONFIG_EXTRA_ENV_SETTINGS \
443 	"netdev=" __stringify(CONFIG_NETDEV) "\0"			\
444 	"ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0"			\
445 	"u-boot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
446 	"u-boot_addr_r=100000\0"					\
447 	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
448 	"update=protect off " __stringify(CONFIG_SYS_FLASH_BASE)	\
449 		" +${filesize};"	\
450 	"erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"	\
451 	"cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE)	\
452 	" ${filesize};"							\
453 	"protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
454 
455 #endif	/* __CONFIG_H */
456