1 /* 2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* U-Boot - Common settings for UniPhier Family */ 8 9 #ifndef __CONFIG_UNIPHIER_COMMON_H__ 10 #define __CONFIG_UNIPHIER_COMMON_H__ 11 12 #define CONFIG_I2C_EEPROM 13 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 14 15 #define CONFIG_SMC911X 16 17 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ 18 #define CONFIG_SMC911X_BASE 0 19 #define CONFIG_SMC911X_32_BIT 20 21 /*----------------------------------------------------------------------- 22 * MMU and Cache Setting 23 *----------------------------------------------------------------------*/ 24 25 /* Comment out the following to enable L1 cache */ 26 /* #define CONFIG_SYS_ICACHE_OFF */ 27 /* #define CONFIG_SYS_DCACHE_OFF */ 28 29 #define CONFIG_SYS_CACHELINE_SIZE 32 30 31 /* Comment out the following to disable L2 cache */ 32 #define CONFIG_UNIPHIER_L2CACHE_ON 33 34 #define CONFIG_DISPLAY_CPUINFO 35 #define CONFIG_DISPLAY_BOARDINFO 36 #define CONFIG_MISC_INIT_F 37 #define CONFIG_BOARD_EARLY_INIT_F 38 #define CONFIG_BOARD_EARLY_INIT_R 39 #define CONFIG_BOARD_LATE_INIT 40 41 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 42 43 #define CONFIG_TIMESTAMP 44 45 /* FLASH related */ 46 #define CONFIG_MTD_DEVICE 47 48 /* 49 * uncomment the following to disable FLASH related code. 50 */ 51 /* #define CONFIG_SYS_NO_FLASH */ 52 53 #define CONFIG_FLASH_CFI_DRIVER 54 #define CONFIG_SYS_FLASH_CFI 55 56 #define CONFIG_SYS_MAX_FLASH_SECT 256 57 #define CONFIG_SYS_MONITOR_BASE 0 58 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ 59 #define CONFIG_SYS_FLASH_BASE 0 60 61 /* 62 * flash_toggle does not work for out supoort card. 63 * We need to use flash_status_poll. 64 */ 65 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 66 67 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 68 69 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 70 71 /* serial console configuration */ 72 #define CONFIG_BAUDRATE 115200 73 74 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) 75 #define CONFIG_USE_ARCH_MEMSET 76 #define CONFIG_USE_ARCH_MEMCPY 77 #endif 78 79 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 80 81 #define CONFIG_CMDLINE_EDITING /* add command line history */ 82 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 83 /* Print Buffer Size */ 84 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 85 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 86 /* Boot Argument Buffer Size */ 87 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 88 89 #define CONFIG_CONS_INDEX 1 90 91 /* #define CONFIG_ENV_IS_NOWHERE */ 92 /* #define CONFIG_ENV_IS_IN_NAND */ 93 #define CONFIG_ENV_IS_IN_MMC 94 #define CONFIG_ENV_OFFSET 0x80000 95 #define CONFIG_ENV_SIZE 0x2000 96 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 97 98 #define CONFIG_SYS_MMC_ENV_DEV 0 99 #define CONFIG_SYS_MMC_ENV_PART 1 100 101 #ifdef CONFIG_ARM64 102 #define CONFIG_ARMV8_MULTIENTRY 103 #define CPU_RELEASE_ADDR 0x80000100 104 #define COUNTER_FREQUENCY 50000000 105 #define CONFIG_GICV3 106 #define GICD_BASE 0x5fe00000 107 #define GICR_BASE 0x5fe80000 108 #else 109 /* Time clock 1MHz */ 110 #define CONFIG_SYS_TIMER_RATE 1000000 111 #endif 112 113 114 #define CONFIG_SYS_MAX_NAND_DEVICE 1 115 #define CONFIG_SYS_NAND_MAX_CHIPS 2 116 #define CONFIG_SYS_NAND_ONFI_DETECTION 117 118 #define CONFIG_NAND_DENALI_ECC_SIZE 1024 119 120 #ifdef CONFIG_ARCH_UNIPHIER_SLD3 121 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 122 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 123 #else 124 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 125 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 126 #endif 127 128 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 129 130 #define CONFIG_SYS_NAND_USE_FLASH_BBT 131 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 132 133 /* USB */ 134 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 135 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 136 #define CONFIG_FAT_WRITE 137 #define CONFIG_DOS_PARTITION 138 139 /* SD/MMC */ 140 #define CONFIG_SUPPORT_EMMC_BOOT 141 #define CONFIG_GENERIC_MMC 142 143 /* memtest works on */ 144 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 145 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) 146 147 #define CONFIG_BOOTDELAY 3 148 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 149 150 /* 151 * Network Configuration 152 */ 153 #define CONFIG_SERVERIP 192.168.11.1 154 #define CONFIG_IPADDR 192.168.11.10 155 #define CONFIG_GATEWAYIP 192.168.11.1 156 #define CONFIG_NETMASK 255.255.255.0 157 158 #define CONFIG_LOADADDR 0x84000000 159 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 160 161 #define CONFIG_CMDLINE_EDITING /* add command line history */ 162 163 #define CONFIG_BOOTCOMMAND "run $bootmode" 164 165 #define CONFIG_ROOTPATH "/nfs/root/path" 166 #define CONFIG_NFSBOOTCOMMAND \ 167 "setenv bootargs $bootargs root=/dev/nfs rw " \ 168 "nfsroot=$serverip:$rootpath " \ 169 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ 170 "run __nfsboot" 171 172 #ifdef CONFIG_FIT 173 #define CONFIG_BOOTFILE "fitImage" 174 #define LINUXBOOT_ENV_SETTINGS \ 175 "fit_addr=0x00100000\0" \ 176 "fit_addr_r=0x84100000\0" \ 177 "fit_size=0x00f00000\0" \ 178 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ 179 "bootm $fit_addr\0" \ 180 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ 181 "bootm $fit_addr_r\0" \ 182 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ 183 "bootm $fit_addr_r\0" \ 184 "__nfsboot=run tftpboot\0" 185 #else 186 #ifdef CONFIG_ARM64 187 #define CONFIG_CMD_BOOTI 188 #define CONFIG_BOOTFILE "Image" 189 #define LINUXBOOT_CMD "booti" 190 #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" 191 #define KERNEL_SIZE "kernel_size=0x00c00000\0" 192 #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" 193 #else 194 #define CONFIG_BOOTFILE "zImage" 195 #define LINUXBOOT_CMD "bootz" 196 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" 197 #define KERNEL_SIZE "kernel_size=0x00800000\0" 198 #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" 199 #endif 200 #define LINUXBOOT_ENV_SETTINGS \ 201 "fdt_addr=0x00100000\0" \ 202 "fdt_addr_r=0x84100000\0" \ 203 "fdt_size=0x00008000\0" \ 204 "kernel_addr=0x00200000\0" \ 205 KERNEL_ADDR_R \ 206 KERNEL_SIZE \ 207 RAMDISK_ADDR \ 208 "ramdisk_addr_r=0x84a00000\0" \ 209 "ramdisk_size=0x00600000\0" \ 210 "ramdisk_file=rootfs.cpio.uboot\0" \ 211 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ 212 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ 213 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ 214 "setexpr kernel_size $kernel_size / 4 &&" \ 215 "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ 216 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ 217 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ 218 "run boot_common\0" \ 219 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ 220 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ 221 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ 222 "run boot_common\0" \ 223 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ 224 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ 225 "tftpboot $fdt_addr_r $fdt_file &&" \ 226 "run boot_common\0" \ 227 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ 228 "tftpboot $fdt_addr_r $fdt_file &&" \ 229 "tftpboot $fdt_addr_r $fdt_file &&" \ 230 "setenv ramdisk_addr_r - &&" \ 231 "run boot_common\0" 232 #endif 233 234 #define CONFIG_EXTRA_ENV_SETTINGS \ 235 "netdev=eth0\0" \ 236 "verify=n\0" \ 237 "nor_base=0x42000000\0" \ 238 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ 239 "tftpboot $tmp_addr u-boot-spl.bin &&" \ 240 "setexpr tmp_addr $nor_base + 0x60000 &&" \ 241 "tftpboot $tmp_addr u-boot.bin\0" \ 242 "emmcupdate=mmcsetn &&" \ 243 "mmc partconf $mmc_first_dev 0 1 1 &&" \ 244 "mmc erase 0 800 &&" \ 245 "tftpboot u-boot-spl.bin &&" \ 246 "mmc write $loadaddr 0 80 &&" \ 247 "tftpboot u-boot.bin &&" \ 248 "mmc write $loadaddr 80 780\0" \ 249 "nandupdate=nand erase 0 0x00100000 &&" \ 250 "tftpboot u-boot-spl.bin &&" \ 251 "nand write $loadaddr 0 0x00010000 &&" \ 252 "tftpboot u-boot.bin &&" \ 253 "nand write $loadaddr 0x00010000 0x000f0000\0" \ 254 LINUXBOOT_ENV_SETTINGS 255 256 #define CONFIG_SYS_BOOTMAPSZ 0x20000000 257 258 #define CONFIG_SYS_SDRAM_BASE 0x80000000 259 #define CONFIG_NR_DRAM_BANKS 2 260 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ 261 #define CONFIG_SYS_MEM_TOP_HIDE 64 262 263 #if defined(CONFIG_ARM64) 264 #define CONFIG_SPL_TEXT_BASE 0x30000000 265 #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ 266 defined(CONFIG_ARCH_UNIPHIER_LD4) || \ 267 defined(CONFIG_ARCH_UNIPHIER_SLD8) 268 #define CONFIG_SPL_TEXT_BASE 0x00040000 269 #else 270 #define CONFIG_SPL_TEXT_BASE 0x00100000 271 #endif 272 273 #if defined(CONFIG_ARCH_UNIPHIER_LD20) 274 #define CONFIG_SPL_STACK (0x3001c000) 275 #else 276 #define CONFIG_SPL_STACK (0x00100000) 277 #endif 278 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) 279 280 #define CONFIG_PANIC_HANG 281 282 #define CONFIG_SPL_FRAMEWORK 283 #define CONFIG_SPL_SERIAL_SUPPORT 284 #define CONFIG_SPL_NOR_SUPPORT 285 #ifndef CONFIG_ARM64 286 #define CONFIG_SPL_NAND_SUPPORT 287 #define CONFIG_SPL_MMC_SUPPORT 288 #endif 289 290 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ 291 #define CONFIG_SPL_LIBGENERIC_SUPPORT 292 293 #define CONFIG_SPL_BOARD_INIT 294 295 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 296 297 /* subtract sizeof(struct image_header) */ 298 #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) 299 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 300 301 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 302 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 303 #define CONFIG_SPL_MAX_SIZE 0x10000 304 #define CONFIG_SPL_BSS_START_ADDR 0x30016000 305 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 306 307 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ 308