1 /* 2 * Copyright (C) 2012-2015 Panasonic Corporation 3 * Copyright (C) 2015-2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* U-Boot - Common settings for UniPhier Family */ 10 11 #ifndef __CONFIG_UNIPHIER_COMMON_H__ 12 #define __CONFIG_UNIPHIER_COMMON_H__ 13 14 #define CONFIG_ARMV7_PSCI_1_0 15 16 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 17 18 #define CONFIG_SMC911X 19 20 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ 21 #define CONFIG_SMC911X_BASE 0 22 #define CONFIG_SMC911X_32_BIT 23 24 /*----------------------------------------------------------------------- 25 * MMU and Cache Setting 26 *----------------------------------------------------------------------*/ 27 28 /* Comment out the following to enable L1 cache */ 29 /* #define CONFIG_SYS_ICACHE_OFF */ 30 /* #define CONFIG_SYS_DCACHE_OFF */ 31 32 #define CONFIG_BOARD_LATE_INIT 33 34 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 35 36 #define CONFIG_TIMESTAMP 37 38 /* FLASH related */ 39 #define CONFIG_MTD_DEVICE 40 41 /* 42 * uncomment the following to disable FLASH related code. 43 */ 44 /* #define CONFIG_SYS_NO_FLASH */ 45 46 #define CONFIG_FLASH_CFI_DRIVER 47 #define CONFIG_SYS_FLASH_CFI 48 49 #define CONFIG_SYS_MAX_FLASH_SECT 256 50 #define CONFIG_SYS_MONITOR_BASE 0 51 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ 52 #define CONFIG_SYS_FLASH_BASE 0 53 54 /* 55 * flash_toggle does not work for out supoort card. 56 * We need to use flash_status_poll. 57 */ 58 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 59 60 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 61 62 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 63 64 /* serial console configuration */ 65 #define CONFIG_BAUDRATE 115200 66 67 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) 68 #define CONFIG_USE_ARCH_MEMSET 69 #define CONFIG_USE_ARCH_MEMCPY 70 #endif 71 72 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 73 74 #define CONFIG_CMDLINE_EDITING /* add command line history */ 75 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 76 /* Print Buffer Size */ 77 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 78 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 79 /* Boot Argument Buffer Size */ 80 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 81 82 #define CONFIG_CONS_INDEX 1 83 84 /* #define CONFIG_ENV_IS_NOWHERE */ 85 /* #define CONFIG_ENV_IS_IN_NAND */ 86 #define CONFIG_ENV_IS_IN_MMC 87 #define CONFIG_ENV_OFFSET 0x80000 88 #define CONFIG_ENV_SIZE 0x2000 89 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 90 91 #define CONFIG_SYS_MMC_ENV_DEV 0 92 #define CONFIG_SYS_MMC_ENV_PART 1 93 94 #ifdef CONFIG_ARM64 95 #define CPU_RELEASE_ADDR 0x80000000 96 #define COUNTER_FREQUENCY 50000000 97 #define CONFIG_GICV3 98 #define GICD_BASE 0x5fe00000 99 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 100 #define GICR_BASE 0x5fe40000 101 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 102 #define GICR_BASE 0x5fe80000 103 #endif 104 #else 105 /* Time clock 1MHz */ 106 #define CONFIG_SYS_TIMER_RATE 1000000 107 #endif 108 109 110 #define CONFIG_SYS_MAX_NAND_DEVICE 1 111 #define CONFIG_SYS_NAND_MAX_CHIPS 2 112 #define CONFIG_SYS_NAND_ONFI_DETECTION 113 114 #define CONFIG_NAND_DENALI_ECC_SIZE 1024 115 116 #ifdef CONFIG_ARCH_UNIPHIER_SLD3 117 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 118 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 119 #else 120 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 121 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 122 #endif 123 124 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 125 126 #define CONFIG_SYS_NAND_USE_FLASH_BBT 127 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 128 129 /* USB */ 130 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 131 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 132 #define CONFIG_FAT_WRITE 133 #define CONFIG_DOS_PARTITION 134 135 /* SD/MMC */ 136 #define CONFIG_SUPPORT_EMMC_BOOT 137 #define CONFIG_GENERIC_MMC 138 139 /* memtest works on */ 140 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 141 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) 142 143 /* 144 * Network Configuration 145 */ 146 #define CONFIG_SERVERIP 192.168.11.1 147 #define CONFIG_IPADDR 192.168.11.10 148 #define CONFIG_GATEWAYIP 192.168.11.1 149 #define CONFIG_NETMASK 255.255.255.0 150 151 #define CONFIG_LOADADDR 0x84000000 152 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 153 154 #define CONFIG_CMDLINE_EDITING /* add command line history */ 155 156 #define CONFIG_BOOTCOMMAND "run $bootmode" 157 158 #define CONFIG_ROOTPATH "/nfs/root/path" 159 #define CONFIG_NFSBOOTCOMMAND \ 160 "setenv bootargs $bootargs root=/dev/nfs rw " \ 161 "nfsroot=$serverip:$rootpath " \ 162 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ 163 "run __nfsboot" 164 165 #ifdef CONFIG_FIT 166 #define CONFIG_BOOTFILE "fitImage" 167 #define LINUXBOOT_ENV_SETTINGS \ 168 "fit_addr=0x00100000\0" \ 169 "fit_addr_r=0x84100000\0" \ 170 "fit_size=0x00f00000\0" \ 171 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ 172 "bootm $fit_addr\0" \ 173 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ 174 "bootm $fit_addr_r\0" \ 175 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ 176 "bootm $fit_addr_r\0" \ 177 "__nfsboot=run tftpboot\0" 178 #else 179 #ifdef CONFIG_ARM64 180 #define CONFIG_BOOTFILE "Image" 181 #define LINUXBOOT_CMD "booti" 182 #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" 183 #define KERNEL_SIZE "kernel_size=0x00c00000\0" 184 #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" 185 #else 186 #define CONFIG_BOOTFILE "zImage" 187 #define LINUXBOOT_CMD "bootz" 188 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" 189 #define KERNEL_SIZE "kernel_size=0x00800000\0" 190 #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" 191 #endif 192 #define LINUXBOOT_ENV_SETTINGS \ 193 "fdt_addr=0x00100000\0" \ 194 "fdt_addr_r=0x84100000\0" \ 195 "fdt_size=0x00008000\0" \ 196 "kernel_addr=0x00200000\0" \ 197 KERNEL_ADDR_R \ 198 KERNEL_SIZE \ 199 RAMDISK_ADDR \ 200 "ramdisk_addr_r=0x84a00000\0" \ 201 "ramdisk_size=0x00600000\0" \ 202 "ramdisk_file=rootfs.cpio.uboot\0" \ 203 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ 204 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ 205 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ 206 "setexpr kernel_size $kernel_size / 4 &&" \ 207 "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ 208 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ 209 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ 210 "run boot_common\0" \ 211 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ 212 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ 213 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ 214 "run boot_common\0" \ 215 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ 216 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ 217 "tftpboot $fdt_addr_r $fdt_file &&" \ 218 "run boot_common\0" \ 219 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ 220 "tftpboot $fdt_addr_r $fdt_file &&" \ 221 "setenv ramdisk_addr_r - &&" \ 222 "run boot_common\0" 223 #endif 224 225 #define CONFIG_EXTRA_ENV_SETTINGS \ 226 "netdev=eth0\0" \ 227 "verify=n\0" \ 228 "nor_base=0x42000000\0" \ 229 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ 230 "tftpboot $tmp_addr u-boot-spl.bin &&" \ 231 "setexpr tmp_addr $nor_base + 0x60000 &&" \ 232 "tftpboot $tmp_addr u-boot.bin\0" \ 233 "emmcupdate=mmcsetn &&" \ 234 "mmc partconf $mmc_first_dev 0 1 1 &&" \ 235 "tftpboot u-boot-spl.bin &&" \ 236 "mmc write $loadaddr 0 80 &&" \ 237 "tftpboot u-boot.bin &&" \ 238 "mmc write $loadaddr 80 780\0" \ 239 "nandupdate=nand erase 0 0x00100000 &&" \ 240 "tftpboot u-boot-spl.bin &&" \ 241 "nand write $loadaddr 0 0x00010000 &&" \ 242 "tftpboot u-boot.bin &&" \ 243 "nand write $loadaddr 0x00010000 0x000f0000\0" \ 244 LINUXBOOT_ENV_SETTINGS 245 246 #define CONFIG_SYS_BOOTMAPSZ 0x20000000 247 248 #define CONFIG_SYS_SDRAM_BASE 0x80000000 249 #define CONFIG_NR_DRAM_BANKS 2 250 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ 251 #define CONFIG_SYS_MEM_TOP_HIDE 64 252 253 #if defined(CONFIG_ARM64) 254 #define CONFIG_SPL_TEXT_BASE 0x30000000 255 #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ 256 defined(CONFIG_ARCH_UNIPHIER_LD4) || \ 257 defined(CONFIG_ARCH_UNIPHIER_SLD8) 258 #define CONFIG_SPL_TEXT_BASE 0x00040000 259 #else 260 #define CONFIG_SPL_TEXT_BASE 0x00100000 261 #endif 262 263 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 264 #define CONFIG_SPL_STACK (0x30014c00) 265 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 266 #define CONFIG_SPL_STACK (0x3001c000) 267 #else 268 #define CONFIG_SPL_STACK (0x00100000) 269 #endif 270 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) 271 272 #define CONFIG_PANIC_HANG 273 274 #define CONFIG_SPL_FRAMEWORK 275 #ifdef CONFIG_ARM64 276 #define CONFIG_SPL_BOARD_LOAD_IMAGE 277 #endif 278 279 #define CONFIG_SPL_BOARD_INIT 280 281 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 282 283 /* subtract sizeof(struct image_header) */ 284 #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) 285 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 286 287 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 288 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 289 #define CONFIG_SPL_MAX_SIZE 0x10000 290 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 291 #define CONFIG_SPL_BSS_START_ADDR 0x30012000 292 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 293 #define CONFIG_SPL_BSS_START_ADDR 0x30016000 294 #endif 295 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 296 297 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ 298