1 /* 2 * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* U-Boot - Common settings for UniPhier Family */ 8 9 #ifndef __CONFIG_UNIPHIER_COMMON_H__ 10 #define __CONFIG_UNIPHIER_COMMON_H__ 11 12 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 13 14 #define CONFIG_SMC911X 15 16 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ 17 #define CONFIG_SMC911X_BASE 0 18 #define CONFIG_SMC911X_32_BIT 19 20 /*----------------------------------------------------------------------- 21 * MMU and Cache Setting 22 *----------------------------------------------------------------------*/ 23 24 /* Comment out the following to enable L1 cache */ 25 /* #define CONFIG_SYS_ICACHE_OFF */ 26 /* #define CONFIG_SYS_DCACHE_OFF */ 27 28 #define CONFIG_SYS_CACHELINE_SIZE 32 29 30 /* Comment out the following to disable L2 cache */ 31 #define CONFIG_UNIPHIER_L2CACHE_ON 32 33 #define CONFIG_DISPLAY_CPUINFO 34 #define CONFIG_DISPLAY_BOARDINFO 35 #define CONFIG_MISC_INIT_F 36 #define CONFIG_BOARD_EARLY_INIT_F 37 #define CONFIG_BOARD_EARLY_INIT_R 38 #define CONFIG_BOARD_LATE_INIT 39 40 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 41 42 #define CONFIG_TIMESTAMP 43 44 /* FLASH related */ 45 #define CONFIG_MTD_DEVICE 46 47 /* 48 * uncomment the following to disable FLASH related code. 49 */ 50 /* #define CONFIG_SYS_NO_FLASH */ 51 52 #define CONFIG_FLASH_CFI_DRIVER 53 #define CONFIG_SYS_FLASH_CFI 54 55 #define CONFIG_SYS_MAX_FLASH_SECT 256 56 #define CONFIG_SYS_MONITOR_BASE 0 57 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ 58 #define CONFIG_SYS_FLASH_BASE 0 59 60 /* 61 * flash_toggle does not work for out supoort card. 62 * We need to use flash_status_poll. 63 */ 64 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 65 66 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 67 68 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 69 70 /* serial console configuration */ 71 #define CONFIG_BAUDRATE 115200 72 73 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) 74 #define CONFIG_USE_ARCH_MEMSET 75 #define CONFIG_USE_ARCH_MEMCPY 76 #endif 77 78 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 79 80 #define CONFIG_CMDLINE_EDITING /* add command line history */ 81 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 82 /* Print Buffer Size */ 83 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 84 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 85 /* Boot Argument Buffer Size */ 86 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 87 88 #define CONFIG_CONS_INDEX 1 89 90 /* #define CONFIG_ENV_IS_NOWHERE */ 91 /* #define CONFIG_ENV_IS_IN_NAND */ 92 #define CONFIG_ENV_IS_IN_MMC 93 #define CONFIG_ENV_OFFSET 0x80000 94 #define CONFIG_ENV_SIZE 0x2000 95 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 96 97 #define CONFIG_SYS_MMC_ENV_DEV 0 98 #define CONFIG_SYS_MMC_ENV_PART 1 99 100 #ifdef CONFIG_ARM64 101 #define CPU_RELEASE_ADDR 0x80000000 102 #define COUNTER_FREQUENCY 50000000 103 #define CONFIG_GICV3 104 #define GICD_BASE 0x5fe00000 105 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 106 #define GICR_BASE 0x5fe40000 107 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 108 #define GICR_BASE 0x5fe80000 109 #endif 110 #else 111 /* Time clock 1MHz */ 112 #define CONFIG_SYS_TIMER_RATE 1000000 113 #endif 114 115 116 #define CONFIG_SYS_MAX_NAND_DEVICE 1 117 #define CONFIG_SYS_NAND_MAX_CHIPS 2 118 #define CONFIG_SYS_NAND_ONFI_DETECTION 119 120 #define CONFIG_NAND_DENALI_ECC_SIZE 1024 121 122 #ifdef CONFIG_ARCH_UNIPHIER_SLD3 123 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 124 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 125 #else 126 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 127 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 128 #endif 129 130 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 131 132 #define CONFIG_SYS_NAND_USE_FLASH_BBT 133 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 134 135 /* USB */ 136 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 137 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 138 #define CONFIG_FAT_WRITE 139 #define CONFIG_DOS_PARTITION 140 141 /* SD/MMC */ 142 #define CONFIG_SUPPORT_EMMC_BOOT 143 #define CONFIG_GENERIC_MMC 144 145 /* memtest works on */ 146 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 147 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) 148 149 /* 150 * Network Configuration 151 */ 152 #define CONFIG_SERVERIP 192.168.11.1 153 #define CONFIG_IPADDR 192.168.11.10 154 #define CONFIG_GATEWAYIP 192.168.11.1 155 #define CONFIG_NETMASK 255.255.255.0 156 157 #define CONFIG_LOADADDR 0x84000000 158 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 159 160 #define CONFIG_CMDLINE_EDITING /* add command line history */ 161 162 #define CONFIG_BOOTCOMMAND "run $bootmode" 163 164 #define CONFIG_ROOTPATH "/nfs/root/path" 165 #define CONFIG_NFSBOOTCOMMAND \ 166 "setenv bootargs $bootargs root=/dev/nfs rw " \ 167 "nfsroot=$serverip:$rootpath " \ 168 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ 169 "run __nfsboot" 170 171 #ifdef CONFIG_FIT 172 #define CONFIG_BOOTFILE "fitImage" 173 #define LINUXBOOT_ENV_SETTINGS \ 174 "fit_addr=0x00100000\0" \ 175 "fit_addr_r=0x84100000\0" \ 176 "fit_size=0x00f00000\0" \ 177 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ 178 "bootm $fit_addr\0" \ 179 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ 180 "bootm $fit_addr_r\0" \ 181 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ 182 "bootm $fit_addr_r\0" \ 183 "__nfsboot=run tftpboot\0" 184 #else 185 #ifdef CONFIG_ARM64 186 #define CONFIG_CMD_BOOTI 187 #define CONFIG_BOOTFILE "Image" 188 #define LINUXBOOT_CMD "booti" 189 #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" 190 #define KERNEL_SIZE "kernel_size=0x00c00000\0" 191 #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" 192 #else 193 #define CONFIG_BOOTFILE "zImage" 194 #define LINUXBOOT_CMD "bootz" 195 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" 196 #define KERNEL_SIZE "kernel_size=0x00800000\0" 197 #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" 198 #endif 199 #define LINUXBOOT_ENV_SETTINGS \ 200 "fdt_addr=0x00100000\0" \ 201 "fdt_addr_r=0x84100000\0" \ 202 "fdt_size=0x00008000\0" \ 203 "kernel_addr=0x00200000\0" \ 204 KERNEL_ADDR_R \ 205 KERNEL_SIZE \ 206 RAMDISK_ADDR \ 207 "ramdisk_addr_r=0x84a00000\0" \ 208 "ramdisk_size=0x00600000\0" \ 209 "ramdisk_file=rootfs.cpio.uboot\0" \ 210 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ 211 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ 212 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ 213 "setexpr kernel_size $kernel_size / 4 &&" \ 214 "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ 215 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ 216 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ 217 "run boot_common\0" \ 218 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ 219 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ 220 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ 221 "run boot_common\0" \ 222 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ 223 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ 224 "tftpboot $fdt_addr_r $fdt_file &&" \ 225 "run boot_common\0" \ 226 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ 227 "tftpboot $fdt_addr_r $fdt_file &&" \ 228 "setenv ramdisk_addr_r - &&" \ 229 "run boot_common\0" 230 #endif 231 232 #define CONFIG_EXTRA_ENV_SETTINGS \ 233 "netdev=eth0\0" \ 234 "verify=n\0" \ 235 "nor_base=0x42000000\0" \ 236 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ 237 "tftpboot $tmp_addr u-boot-spl.bin &&" \ 238 "setexpr tmp_addr $nor_base + 0x60000 &&" \ 239 "tftpboot $tmp_addr u-boot.bin\0" \ 240 "emmcupdate=mmcsetn &&" \ 241 "mmc partconf $mmc_first_dev 0 1 1 &&" \ 242 "tftpboot u-boot-spl.bin &&" \ 243 "mmc write $loadaddr 0 80 &&" \ 244 "tftpboot u-boot.bin &&" \ 245 "mmc write $loadaddr 80 780\0" \ 246 "nandupdate=nand erase 0 0x00100000 &&" \ 247 "tftpboot u-boot-spl.bin &&" \ 248 "nand write $loadaddr 0 0x00010000 &&" \ 249 "tftpboot u-boot.bin &&" \ 250 "nand write $loadaddr 0x00010000 0x000f0000\0" \ 251 LINUXBOOT_ENV_SETTINGS 252 253 #define CONFIG_SYS_BOOTMAPSZ 0x20000000 254 255 #define CONFIG_SYS_SDRAM_BASE 0x80000000 256 #define CONFIG_NR_DRAM_BANKS 2 257 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ 258 #define CONFIG_SYS_MEM_TOP_HIDE 64 259 260 #if defined(CONFIG_ARM64) 261 #define CONFIG_SPL_TEXT_BASE 0x30000000 262 #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ 263 defined(CONFIG_ARCH_UNIPHIER_LD4) || \ 264 defined(CONFIG_ARCH_UNIPHIER_SLD8) 265 #define CONFIG_SPL_TEXT_BASE 0x00040000 266 #else 267 #define CONFIG_SPL_TEXT_BASE 0x00100000 268 #endif 269 270 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 271 #define CONFIG_SPL_STACK (0x30014c00) 272 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 273 #define CONFIG_SPL_STACK (0x3001c000) 274 #else 275 #define CONFIG_SPL_STACK (0x00100000) 276 #endif 277 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) 278 279 #define CONFIG_PANIC_HANG 280 281 #define CONFIG_SPL_FRAMEWORK 282 #define CONFIG_SPL_SERIAL_SUPPORT 283 #define CONFIG_SPL_NOR_SUPPORT 284 #ifdef CONFIG_ARM64 285 #define CONFIG_SPL_BOARD_LOAD_IMAGE 286 #else 287 #define CONFIG_SPL_NAND_SUPPORT 288 #define CONFIG_SPL_MMC_SUPPORT 289 #endif 290 291 #define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ 292 #define CONFIG_SPL_LIBGENERIC_SUPPORT 293 294 #define CONFIG_SPL_BOARD_INIT 295 296 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 297 298 /* subtract sizeof(struct image_header) */ 299 #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) 300 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 301 302 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 303 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 304 #define CONFIG_SPL_MAX_SIZE 0x10000 305 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 306 #define CONFIG_SPL_BSS_START_ADDR 0x30012000 307 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 308 #define CONFIG_SPL_BSS_START_ADDR 0x30016000 309 #endif 310 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 311 312 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ 313