1 /* 2 * Copyright (C) 2012-2015 Panasonic Corporation 3 * Copyright (C) 2015-2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* U-Boot - Common settings for UniPhier Family */ 10 11 #ifndef __CONFIG_UNIPHIER_COMMON_H__ 12 #define __CONFIG_UNIPHIER_COMMON_H__ 13 14 #define CONFIG_ARMV7_PSCI_1_0 15 16 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 17 18 /*----------------------------------------------------------------------- 19 * MMU and Cache Setting 20 *----------------------------------------------------------------------*/ 21 22 /* Comment out the following to enable L1 cache */ 23 /* #define CONFIG_SYS_ICACHE_OFF */ 24 /* #define CONFIG_SYS_DCACHE_OFF */ 25 26 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 27 28 #define CONFIG_TIMESTAMP 29 30 /* FLASH related */ 31 #define CONFIG_MTD_DEVICE 32 33 #define CONFIG_SMC911X_32_BIT 34 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ 35 #define CONFIG_SMC911X_BASE 0 36 37 #ifdef CONFIG_MICRO_SUPPORT_CARD 38 #define CONFIG_SMC911X 39 #endif 40 41 #define CONFIG_FLASH_CFI_DRIVER 42 #define CONFIG_SYS_FLASH_CFI 43 44 #define CONFIG_SYS_MAX_FLASH_SECT 256 45 #define CONFIG_SYS_MONITOR_BASE 0 46 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ 47 #define CONFIG_SYS_FLASH_BASE 0 48 49 /* 50 * flash_toggle does not work for our support card. 51 * We need to use flash_status_poll. 52 */ 53 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 54 55 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 56 57 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 58 59 /* serial console configuration */ 60 61 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 62 63 #define CONFIG_CMDLINE_EDITING /* add command line history */ 64 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 65 /* Print Buffer Size */ 66 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 67 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 68 /* Boot Argument Buffer Size */ 69 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 70 71 #define CONFIG_CONS_INDEX 1 72 73 #define CONFIG_ENV_OFFSET 0x100000 74 #define CONFIG_ENV_SIZE 0x2000 75 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 76 77 #define CONFIG_SYS_MMC_ENV_DEV 0 78 #define CONFIG_SYS_MMC_ENV_PART 1 79 80 #if !defined(CONFIG_ARM64) 81 /* Time clock 1MHz */ 82 #define CONFIG_SYS_TIMER_RATE 1000000 83 #endif 84 85 #define CONFIG_SYS_MAX_NAND_DEVICE 1 86 #define CONFIG_SYS_NAND_MAX_CHIPS 2 87 #define CONFIG_SYS_NAND_ONFI_DETECTION 88 89 #define CONFIG_NAND_DENALI_ECC_SIZE 1024 90 91 #ifdef CONFIG_ARCH_UNIPHIER_SLD3 92 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 93 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 94 #else 95 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 96 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 97 #endif 98 99 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 100 101 #define CONFIG_SYS_NAND_USE_FLASH_BBT 102 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 103 104 /* USB */ 105 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 106 107 /* SD/MMC */ 108 #define CONFIG_SUPPORT_EMMC_BOOT 109 110 /* memtest works on */ 111 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 112 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) 113 114 /* 115 * Network Configuration 116 */ 117 #define CONFIG_SERVERIP 192.168.11.1 118 #define CONFIG_IPADDR 192.168.11.10 119 #define CONFIG_GATEWAYIP 192.168.11.1 120 #define CONFIG_NETMASK 255.255.255.0 121 122 #define CONFIG_LOADADDR 0x84000000 123 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 124 125 #define CONFIG_CMDLINE_EDITING /* add command line history */ 126 127 #if defined(CONFIG_ARM64) 128 /* ARM Trusted Firmware */ 129 #define BOOT_IMAGES \ 130 "second_image=unph_bl.bin\0" \ 131 "third_image=fip.bin\0" 132 #else 133 #define BOOT_IMAGES \ 134 "second_image=u-boot-spl.bin\0" \ 135 "third_image=u-boot.bin\0" 136 #endif 137 138 #define CONFIG_BOOTCOMMAND "run $bootmode" 139 140 #define CONFIG_ROOTPATH "/nfs/root/path" 141 #define CONFIG_NFSBOOTCOMMAND \ 142 "setenv bootargs $bootargs root=/dev/nfs rw " \ 143 "nfsroot=$serverip:$rootpath " \ 144 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ 145 "run __nfsboot" 146 147 #ifdef CONFIG_FIT 148 #define CONFIG_BOOTFILE "fitImage" 149 #define LINUXBOOT_ENV_SETTINGS \ 150 "fit_addr=0x00100000\0" \ 151 "fit_addr_r=0x84100000\0" \ 152 "fit_size=0x00f00000\0" \ 153 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ 154 "bootm $fit_addr\0" \ 155 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ 156 "bootm $fit_addr_r\0" \ 157 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ 158 "bootm $fit_addr_r\0" \ 159 "__nfsboot=run tftpboot\0" 160 #else 161 #ifdef CONFIG_ARM64 162 #define CONFIG_BOOTFILE "Image.gz" 163 #define LINUXBOOT_CMD "booti" 164 #define KERNEL_ADDR_LOAD "kernel_addr_load=0x84200000\0" 165 #define KERNEL_ADDR_R "kernel_addr_r=0x82080000\0" 166 #else 167 #define CONFIG_BOOTFILE "zImage" 168 #define LINUXBOOT_CMD "bootz" 169 #define KERNEL_ADDR_LOAD "kernel_addr_load=0x80208000\0" 170 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" 171 #endif 172 #define LINUXBOOT_ENV_SETTINGS \ 173 "fdt_addr=0x00100000\0" \ 174 "fdt_addr_r=0x84100000\0" \ 175 "fdt_size=0x00008000\0" \ 176 "kernel_addr=0x00200000\0" \ 177 KERNEL_ADDR_LOAD \ 178 KERNEL_ADDR_R \ 179 "kernel_size=0x00800000\0" \ 180 "ramdisk_addr=0x00a00000\0" \ 181 "ramdisk_addr_r=0x84a00000\0" \ 182 "ramdisk_size=0x00600000\0" \ 183 "ramdisk_file=rootfs.cpio.uboot\0" \ 184 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \ 185 "if test $kernel_addr_load = $kernel_addr_r; then " \ 186 "true; " \ 187 "else " \ 188 "unzip $kernel_addr_load $kernel_addr_r; " \ 189 "fi && " \ 190 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ 191 "norboot=setexpr kernel_addr_nor $nor_base + $kernel_addr && " \ 192 "setexpr kernel_size_div4 $kernel_size / 4 && " \ 193 "cp $kernel_addr_nor $kernel_addr_load $kernel_size_div4 && " \ 194 "setexpr ramdisk_addr_nor $nor_base + $ramdisk_addr && " \ 195 "setexpr ramdisk_size_div4 $ramdisk_size / 4 && " \ 196 "cp $ramdisk_addr_nor $ramdisk_addr_r $ramdisk_size_div4 && " \ 197 "setexpr fdt_addr_nor $nor_base + $fdt_addr && " \ 198 "setexpr fdt_size_div4 $fdt_size / 4 && " \ 199 "cp $fdt_addr_nor $fdt_addr_r $fdt_size_div4 && " \ 200 "run boot_common\0" \ 201 "nandboot=nand read $kernel_addr_load $kernel_addr $kernel_size && " \ 202 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ 203 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ 204 "run boot_common\0" \ 205 "tftpboot=tftpboot $kernel_addr_load $bootfile && " \ 206 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ 207 "tftpboot $fdt_addr_r $fdt_file &&" \ 208 "run boot_common\0" \ 209 "__nfsboot=tftpboot $kernel_addr_load $bootfile && " \ 210 "tftpboot $fdt_addr_r $fdt_file &&" \ 211 "setenv ramdisk_addr_r - &&" \ 212 "run boot_common\0" 213 #endif 214 215 #define CONFIG_EXTRA_ENV_SETTINGS \ 216 "netdev=eth0\0" \ 217 "verify=n\0" \ 218 "initrd_high=0xffffffffffffffff\0" \ 219 "nor_base=0x42000000\0" \ 220 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ 221 "tftpboot $tmp_addr $second_image && " \ 222 "setexpr tmp_addr $nor_base + 0x70000 && " \ 223 "tftpboot $tmp_addr $third_image\0" \ 224 "emmcupdate=mmcsetn &&" \ 225 "mmc partconf $mmc_first_dev 0 1 1 &&" \ 226 "tftpboot $second_image && " \ 227 "mmc write $loadaddr 0 100 && " \ 228 "tftpboot $third_image && " \ 229 "mmc write $loadaddr 100 700\0" \ 230 "nandupdate=nand erase 0 0x00100000 &&" \ 231 "tftpboot $second_image && " \ 232 "nand write $loadaddr 0 0x00020000 && " \ 233 "tftpboot $third_image && " \ 234 "nand write $loadaddr 0x00020000 0x000e0000\0" \ 235 "usbupdate=usb start &&" \ 236 "tftpboot $second_image && " \ 237 "usb write $loadaddr 0 100 && " \ 238 "tftpboot $third_image && " \ 239 "usb write $loadaddr 100 700\0" \ 240 BOOT_IMAGES \ 241 LINUXBOOT_ENV_SETTINGS 242 243 #define CONFIG_SYS_BOOTMAPSZ 0x20000000 244 245 #define CONFIG_SYS_SDRAM_BASE 0x80000000 246 #define CONFIG_NR_DRAM_BANKS 3 247 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ 248 #define CONFIG_SYS_MEM_TOP_HIDE 64 249 250 #define CONFIG_PANIC_HANG 251 252 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) 253 254 /* only for SPL */ 255 #if defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ 256 defined(CONFIG_ARCH_UNIPHIER_LD4) || \ 257 defined(CONFIG_ARCH_UNIPHIER_SLD8) 258 #define CONFIG_SPL_TEXT_BASE 0x00040000 259 #else 260 #define CONFIG_SPL_TEXT_BASE 0x00100000 261 #endif 262 263 #define CONFIG_SPL_STACK (0x00100000) 264 265 #define CONFIG_SPL_FRAMEWORK 266 267 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 268 269 /* subtract sizeof(struct image_header) */ 270 #define CONFIG_SYS_UBOOT_BASE (0x70000 - 0x40) 271 272 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 273 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 274 #define CONFIG_SPL_MAX_SIZE 0x10000 275 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 276 277 #define CONFIG_SPL_PAD_TO 0x20000 278 279 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ 280