1 /* 2 * Copyright (C) 2012-2015 Panasonic Corporation 3 * Copyright (C) 2015-2016 Socionext Inc. 4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* U-Boot - Common settings for UniPhier Family */ 10 11 #ifndef __CONFIG_UNIPHIER_COMMON_H__ 12 #define __CONFIG_UNIPHIER_COMMON_H__ 13 14 #define CONFIG_ARMV7_PSCI_1_0 15 16 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 17 18 #define CONFIG_SMC911X 19 20 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */ 21 #define CONFIG_SMC911X_BASE 0 22 #define CONFIG_SMC911X_32_BIT 23 24 /*----------------------------------------------------------------------- 25 * MMU and Cache Setting 26 *----------------------------------------------------------------------*/ 27 28 /* Comment out the following to enable L1 cache */ 29 /* #define CONFIG_SYS_ICACHE_OFF */ 30 /* #define CONFIG_SYS_DCACHE_OFF */ 31 32 #define CONFIG_DISPLAY_CPUINFO 33 #define CONFIG_DISPLAY_BOARDINFO 34 #define CONFIG_BOARD_LATE_INIT 35 36 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 37 38 #define CONFIG_TIMESTAMP 39 40 /* FLASH related */ 41 #define CONFIG_MTD_DEVICE 42 43 /* 44 * uncomment the following to disable FLASH related code. 45 */ 46 /* #define CONFIG_SYS_NO_FLASH */ 47 48 #define CONFIG_FLASH_CFI_DRIVER 49 #define CONFIG_SYS_FLASH_CFI 50 51 #define CONFIG_SYS_MAX_FLASH_SECT 256 52 #define CONFIG_SYS_MONITOR_BASE 0 53 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */ 54 #define CONFIG_SYS_FLASH_BASE 0 55 56 /* 57 * flash_toggle does not work for out supoort card. 58 * We need to use flash_status_poll. 59 */ 60 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 61 62 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 63 64 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 65 66 /* serial console configuration */ 67 #define CONFIG_BAUDRATE 115200 68 69 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) 70 #define CONFIG_USE_ARCH_MEMSET 71 #define CONFIG_USE_ARCH_MEMCPY 72 #endif 73 74 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 75 76 #define CONFIG_CMDLINE_EDITING /* add command line history */ 77 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 78 /* Print Buffer Size */ 79 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 80 #define CONFIG_SYS_MAXARGS 16 /* max number of command */ 81 /* Boot Argument Buffer Size */ 82 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 83 84 #define CONFIG_CONS_INDEX 1 85 86 /* #define CONFIG_ENV_IS_NOWHERE */ 87 /* #define CONFIG_ENV_IS_IN_NAND */ 88 #define CONFIG_ENV_IS_IN_MMC 89 #define CONFIG_ENV_OFFSET 0x80000 90 #define CONFIG_ENV_SIZE 0x2000 91 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ 92 93 #define CONFIG_SYS_MMC_ENV_DEV 0 94 #define CONFIG_SYS_MMC_ENV_PART 1 95 96 #ifdef CONFIG_ARM64 97 #define CPU_RELEASE_ADDR 0x80000000 98 #define COUNTER_FREQUENCY 50000000 99 #define CONFIG_GICV3 100 #define GICD_BASE 0x5fe00000 101 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 102 #define GICR_BASE 0x5fe40000 103 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 104 #define GICR_BASE 0x5fe80000 105 #endif 106 #else 107 /* Time clock 1MHz */ 108 #define CONFIG_SYS_TIMER_RATE 1000000 109 #endif 110 111 112 #define CONFIG_SYS_MAX_NAND_DEVICE 1 113 #define CONFIG_SYS_NAND_MAX_CHIPS 2 114 #define CONFIG_SYS_NAND_ONFI_DETECTION 115 116 #define CONFIG_NAND_DENALI_ECC_SIZE 1024 117 118 #ifdef CONFIG_ARCH_UNIPHIER_SLD3 119 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 120 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 121 #else 122 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 123 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 124 #endif 125 126 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) 127 128 #define CONFIG_SYS_NAND_USE_FLASH_BBT 129 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 130 131 /* USB */ 132 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 133 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4 134 #define CONFIG_FAT_WRITE 135 #define CONFIG_DOS_PARTITION 136 137 /* SD/MMC */ 138 #define CONFIG_SUPPORT_EMMC_BOOT 139 #define CONFIG_GENERIC_MMC 140 141 /* memtest works on */ 142 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 143 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) 144 145 /* 146 * Network Configuration 147 */ 148 #define CONFIG_SERVERIP 192.168.11.1 149 #define CONFIG_IPADDR 192.168.11.10 150 #define CONFIG_GATEWAYIP 192.168.11.1 151 #define CONFIG_NETMASK 255.255.255.0 152 153 #define CONFIG_LOADADDR 0x84000000 154 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 155 156 #define CONFIG_CMDLINE_EDITING /* add command line history */ 157 158 #define CONFIG_BOOTCOMMAND "run $bootmode" 159 160 #define CONFIG_ROOTPATH "/nfs/root/path" 161 #define CONFIG_NFSBOOTCOMMAND \ 162 "setenv bootargs $bootargs root=/dev/nfs rw " \ 163 "nfsroot=$serverip:$rootpath " \ 164 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ 165 "run __nfsboot" 166 167 #ifdef CONFIG_FIT 168 #define CONFIG_BOOTFILE "fitImage" 169 #define LINUXBOOT_ENV_SETTINGS \ 170 "fit_addr=0x00100000\0" \ 171 "fit_addr_r=0x84100000\0" \ 172 "fit_size=0x00f00000\0" \ 173 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ 174 "bootm $fit_addr\0" \ 175 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ 176 "bootm $fit_addr_r\0" \ 177 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ 178 "bootm $fit_addr_r\0" \ 179 "__nfsboot=run tftpboot\0" 180 #else 181 #ifdef CONFIG_ARM64 182 #define CONFIG_BOOTFILE "Image" 183 #define LINUXBOOT_CMD "booti" 184 #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" 185 #define KERNEL_SIZE "kernel_size=0x00c00000\0" 186 #define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" 187 #else 188 #define CONFIG_BOOTFILE "zImage" 189 #define LINUXBOOT_CMD "bootz" 190 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" 191 #define KERNEL_SIZE "kernel_size=0x00800000\0" 192 #define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" 193 #endif 194 #define LINUXBOOT_ENV_SETTINGS \ 195 "fdt_addr=0x00100000\0" \ 196 "fdt_addr_r=0x84100000\0" \ 197 "fdt_size=0x00008000\0" \ 198 "kernel_addr=0x00200000\0" \ 199 KERNEL_ADDR_R \ 200 KERNEL_SIZE \ 201 RAMDISK_ADDR \ 202 "ramdisk_addr_r=0x84a00000\0" \ 203 "ramdisk_size=0x00600000\0" \ 204 "ramdisk_file=rootfs.cpio.uboot\0" \ 205 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ 206 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ 207 "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ 208 "setexpr kernel_size $kernel_size / 4 &&" \ 209 "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ 210 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ 211 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ 212 "run boot_common\0" \ 213 "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ 214 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ 215 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ 216 "run boot_common\0" \ 217 "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ 218 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ 219 "tftpboot $fdt_addr_r $fdt_file &&" \ 220 "run boot_common\0" \ 221 "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \ 222 "tftpboot $fdt_addr_r $fdt_file &&" \ 223 "setenv ramdisk_addr_r - &&" \ 224 "run boot_common\0" 225 #endif 226 227 #define CONFIG_EXTRA_ENV_SETTINGS \ 228 "netdev=eth0\0" \ 229 "verify=n\0" \ 230 "nor_base=0x42000000\0" \ 231 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ 232 "tftpboot $tmp_addr u-boot-spl.bin &&" \ 233 "setexpr tmp_addr $nor_base + 0x60000 &&" \ 234 "tftpboot $tmp_addr u-boot.bin\0" \ 235 "emmcupdate=mmcsetn &&" \ 236 "mmc partconf $mmc_first_dev 0 1 1 &&" \ 237 "tftpboot u-boot-spl.bin &&" \ 238 "mmc write $loadaddr 0 80 &&" \ 239 "tftpboot u-boot.bin &&" \ 240 "mmc write $loadaddr 80 780\0" \ 241 "nandupdate=nand erase 0 0x00100000 &&" \ 242 "tftpboot u-boot-spl.bin &&" \ 243 "nand write $loadaddr 0 0x00010000 &&" \ 244 "tftpboot u-boot.bin &&" \ 245 "nand write $loadaddr 0x00010000 0x000f0000\0" \ 246 LINUXBOOT_ENV_SETTINGS 247 248 #define CONFIG_SYS_BOOTMAPSZ 0x20000000 249 250 #define CONFIG_SYS_SDRAM_BASE 0x80000000 251 #define CONFIG_NR_DRAM_BANKS 2 252 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */ 253 #define CONFIG_SYS_MEM_TOP_HIDE 64 254 255 #if defined(CONFIG_ARM64) 256 #define CONFIG_SPL_TEXT_BASE 0x30000000 257 #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ 258 defined(CONFIG_ARCH_UNIPHIER_LD4) || \ 259 defined(CONFIG_ARCH_UNIPHIER_SLD8) 260 #define CONFIG_SPL_TEXT_BASE 0x00040000 261 #else 262 #define CONFIG_SPL_TEXT_BASE 0x00100000 263 #endif 264 265 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 266 #define CONFIG_SPL_STACK (0x30014c00) 267 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 268 #define CONFIG_SPL_STACK (0x3001c000) 269 #else 270 #define CONFIG_SPL_STACK (0x00100000) 271 #endif 272 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) 273 274 #define CONFIG_PANIC_HANG 275 276 #define CONFIG_SPL_FRAMEWORK 277 #ifdef CONFIG_ARM64 278 #define CONFIG_SPL_BOARD_LOAD_IMAGE 279 #endif 280 281 #define CONFIG_SPL_BOARD_INIT 282 283 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000 284 285 /* subtract sizeof(struct image_header) */ 286 #define CONFIG_SYS_UBOOT_BASE (0x60000 - 0x40) 287 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80 288 289 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 290 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 291 #define CONFIG_SPL_MAX_SIZE 0x10000 292 #if defined(CONFIG_ARCH_UNIPHIER_LD11) 293 #define CONFIG_SPL_BSS_START_ADDR 0x30012000 294 #elif defined(CONFIG_ARCH_UNIPHIER_LD20) 295 #define CONFIG_SPL_BSS_START_ADDR 0x30016000 296 #endif 297 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 298 299 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */ 300