1 /* 2 * include/configs/ulcb.h 3 * This file is ULCB board configuration. 4 * 5 * Copyright (C) 2017 Renesas Electronics Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __ULCB_H 11 #define __ULCB_H 12 13 #undef DEBUG 14 15 #include "rcar-gen3-common.h" 16 17 /* M3 ULCB has 2 banks, each with 1 GiB of RAM */ 18 #if defined(CONFIG_R8A7796) 19 #undef PHYS_SDRAM_1_SIZE 20 #undef PHYS_SDRAM_2_SIZE 21 #define PHYS_SDRAM_1_SIZE (0x40000000u - DRAM_RSV_SIZE) 22 #define PHYS_SDRAM_2_SIZE 0x40000000u 23 #endif 24 25 /* SCIF */ 26 #define CONFIG_CONS_SCIF2 27 #define CONFIG_CONS_INDEX 2 28 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ 29 30 /* [A] Hyper Flash */ 31 /* use to RPC(SPI Multi I/O Bus Controller) */ 32 33 /* Ethernet RAVB */ 34 #define CONFIG_BITBANGMII 35 #define CONFIG_BITBANGMII_MULTI 36 37 /* Board Clock */ 38 /* XTAL_CLK : 33.33MHz */ 39 #define RCAR_XTAL_CLK 33333333u 40 #define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK 41 /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ 42 /* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ 43 #define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) 44 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) 45 #define CONFIG_S3D2_CLK_FREQ (266666666u/2) 46 #define CONFIG_S3D4_CLK_FREQ (266666666u/4) 47 48 /* Generic Timer Definitions (use in assembler source) */ 49 #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ 50 51 /* CPLD SPI */ 52 #define CONFIG_CMD_SPI 53 #define CONFIG_SOFT_SPI 54 #define SPI_DELAY udelay(0) 55 #define SPI_SDA(val) ulcb_softspi_sda(val) 56 #define SPI_SCL(val) ulcb_softspi_scl(val) 57 #define SPI_READ ulcb_softspi_read() 58 #ifndef __ASSEMBLY__ 59 void ulcb_softspi_sda(int); 60 void ulcb_softspi_scl(int); 61 unsigned char ulcb_softspi_read(void); 62 #endif 63 64 /* i2c */ 65 #define CONFIG_SYS_I2C 66 #define CONFIG_SYS_I2C_SH 67 #define CONFIG_SYS_I2C_SLAVE 0x60 68 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 69 #define CONFIG_SYS_I2C_SH_SPEED0 400000 70 #define CONFIG_SH_I2C_DATA_HIGH 4 71 #define CONFIG_SH_I2C_DATA_LOW 5 72 #define CONFIG_SH_I2C_CLOCK 10000000 73 74 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 75 76 /* SDHI */ 77 #define CONFIG_SH_SDHI_FREQ 200000000 78 79 /* Environment in eMMC, at the end of 2nd "boot sector" */ 80 #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) 81 #define CONFIG_SYS_MMC_ENV_DEV 1 82 #define CONFIG_SYS_MMC_ENV_PART 2 83 84 #endif /* __ULCB_H */ 85