1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2006 Freescale Semiconductor, Inc. 4 * Dave Liu <daveliu@freescale.com> 5 * 6 * Copyright (C) 2007 Logic Product Development, Inc. 7 * Peter Barada <peterb@logicpd.com> 8 * 9 * Copyright (C) 2007 MontaVista Software, Inc. 10 * Anton Vorontsov <avorontsov@ru.mvista.com> 11 * 12 * (C) Copyright 2008 13 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 14 * 15 * (C) Copyright 2010-2013 16 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com 17 * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com 18 */ 19 20 #ifndef __CONFIG_H 21 #define __CONFIG_H 22 23 /* 24 * High Level Configuration Options 25 */ 26 #if defined(CONFIG_KMSUPX5) 27 #define CONFIG_KM_BOARD_NAME "kmsupx5" 28 #define CONFIG_HOSTNAME "kmsupx5" 29 #elif defined(CONFIG_TUGE1) 30 #define CONFIG_KM_BOARD_NAME "tuge1" 31 #define CONFIG_HOSTNAME "tuge1" 32 #elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */ 33 #define CONFIG_KM_BOARD_NAME "tuxx1" 34 #define CONFIG_HOSTNAME "tuxx1" 35 #elif defined(CONFIG_KMOPTI2) 36 #define CONFIG_KM_BOARD_NAME "kmopti2" 37 #define CONFIG_HOSTNAME "kmopti2" 38 #elif defined(CONFIG_KMTEPR2) 39 #define CONFIG_KM_BOARD_NAME "kmtepr2" 40 #define CONFIG_HOSTNAME "kmtepr2" 41 #else 42 #error ("Board not supported") 43 #endif 44 45 /* include common defines/options for all 8321 Keymile boards */ 46 #include "km/km8321-common.h" 47 48 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ 49 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ 50 #if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2) 51 #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ 52 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ 53 #endif 54 55 /* 56 * Init Local Bus Memory Controller: 57 * Device on board 58 * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 59 * ----------------------------------------------------------------------------- 60 * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE 61 * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) 62 * 63 * Device on board (continued) 64 * Bank Bus Machine PortSz Size KMTEPR2 65 * ----------------------------------------------------------------------------- 66 * 2 Local GPCM 8 bit 256MB NVRAM 67 * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) 68 */ 69 70 #if defined(CONFIG_KMTEPRO2) 71 /* 72 * Configuration for C2 (NVRAM) on the local bus 73 */ 74 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE 75 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 76 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ 77 BR_PS_8 | \ 78 BR_MS_GPCM | \ 79 BR_V) 80 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ 81 OR_GPCM_CSNT | \ 82 OR_GPCM_ACS_DIV2 | \ 83 OR_GPCM_XACS | \ 84 OR_GPCM_SCY_2 | \ 85 OR_GPCM_TRLX_SET | \ 86 OR_GPCM_EHTR_SET | \ 87 OR_GPCM_EAD) 88 #else 89 /* 90 * Configuration for C2 on the local bus 91 */ 92 /* Window base at flash base */ 93 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE 94 /* Window size: 256 MB */ 95 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 96 97 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ 98 BR_PS_8 | \ 99 BR_MS_GPCM | \ 100 BR_V) 101 102 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ 103 OR_GPCM_CSNT | \ 104 OR_GPCM_ACS_DIV4 | \ 105 OR_GPCM_SCY_2 | \ 106 OR_GPCM_TRLX_SET | \ 107 OR_GPCM_EHTR_CLEAR | \ 108 OR_GPCM_EAD) 109 #endif 110 111 #if defined(CONFIG_TUXX1) 112 /* 113 * Configuration for C3 on the local bus 114 */ 115 /* Access window base at PINC3 base */ 116 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE 117 /* Window size: 256 MB */ 118 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 119 120 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ 121 BR_PS_8 | \ 122 BR_MS_GPCM | \ 123 BR_V) 124 125 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ 126 OR_GPCM_CSNT | \ 127 OR_GPCM_ACS_DIV2 | \ 128 OR_GPCM_SCY_2 | \ 129 OR_GPCM_TRLX_SET | \ 130 OR_GPCM_EHTR_CLEAR) 131 132 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 133 0x0000c000 | \ 134 MxMR_WLFx_2X) 135 #endif 136 137 #if defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2) 138 /* 139 * Configuration for C3 on the local bus 140 */ 141 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE 142 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 143 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ 144 BR_PS_16 | \ 145 BR_MS_GPCM | \ 146 BR_V) 147 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ 148 OR_GPCM_SCY_4 | \ 149 OR_GPCM_TRLX_CLEAR | \ 150 OR_GPCM_EHTR_CLEAR) 151 #endif 152 153 /* 154 * MMU Setup 155 */ 156 /* APP1: icache cacheable, but dcache-inhibit and guarded */ 157 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ 158 BATL_PP_RW | \ 159 BATL_MEMCOHERENCE) 160 /* 512M should also include APP2... */ 161 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ 162 BATU_BL_256M | \ 163 BATU_VS | \ 164 BATU_VP) 165 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ 166 BATL_PP_RW | \ 167 BATL_CACHEINHIBIT | \ 168 BATL_GUARDEDSTORAGE) 169 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 170 171 #if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5) 172 #define CONFIG_SYS_IBAT6L (0) 173 #define CONFIG_SYS_IBAT6U (0) 174 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 175 #else 176 /* APP2: icache cacheable, but dcache-inhibit and guarded */ 177 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ 178 BATL_PP_RW | \ 179 BATL_MEMCOHERENCE) 180 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ 181 BATU_BL_256M | \ 182 BATU_VS | \ 183 BATU_VP) 184 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ 185 BATL_PP_RW | \ 186 BATL_CACHEINHIBIT | \ 187 BATL_GUARDEDSTORAGE) 188 #endif 189 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 190 191 #define CONFIG_SYS_IBAT7L (0) 192 #define CONFIG_SYS_IBAT7U (0) 193 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 194 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 195 196 #endif /* __CONFIG_H */ 197