1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2008 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * (C) Copyright 2010-2013 15 * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com 16 * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com 17 * 18 * SPDX-License-Identifier: GPL-2.0+ 19 */ 20 21 #ifndef __CONFIG_H 22 #define __CONFIG_H 23 24 /* 25 * High Level Configuration Options 26 */ 27 #if defined(CONFIG_KMSUPX5) 28 #define CONFIG_KM_BOARD_NAME "kmsupx5" 29 #define CONFIG_HOSTNAME kmsupx5 30 #elif defined(CONFIG_TUGE1) 31 #define CONFIG_KM_BOARD_NAME "tuge1" 32 #define CONFIG_HOSTNAME tuge1 33 #elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */ 34 #define CONFIG_KM_BOARD_NAME "tuxx1" 35 #define CONFIG_HOSTNAME tuxx1 36 #elif defined(CONFIG_KMOPTI2) 37 #define CONFIG_KM_BOARD_NAME "kmopti2" 38 #define CONFIG_HOSTNAME kmopti2 39 #elif defined(CONFIG_KMTEPR2) 40 #define CONFIG_KM_BOARD_NAME "kmtepr2" 41 #define CONFIG_HOSTNAME kmtepr2 42 #else 43 #error ("Board not supported") 44 #endif 45 46 #define CONFIG_SYS_TEXT_BASE 0xF0000000 47 48 /* include common defines/options for all 8321 Keymile boards */ 49 #include "km/km8321-common.h" 50 51 #define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */ 52 #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ 53 #if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2) 54 #define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */ 55 #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ 56 #endif 57 58 /* 59 * Init Local Bus Memory Controller: 60 * Device on board 61 * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2 62 * ----------------------------------------------------------------------------- 63 * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE 64 * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit) 65 * 66 * Device on board (continued) 67 * Bank Bus Machine PortSz Size KMTEPR2 68 * ----------------------------------------------------------------------------- 69 * 2 Local GPCM 8 bit 256MB NVRAM 70 * 3 Local GPCM 8 bit 256MB TEP2 (16 bit) 71 */ 72 73 #if defined(CONFIG_KMTEPRO2) 74 /* 75 * Configuration for C2 (NVRAM) on the local bus 76 */ 77 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE 78 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 79 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ 80 BR_PS_8 | \ 81 BR_MS_GPCM | \ 82 BR_V) 83 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ 84 OR_GPCM_CSNT | \ 85 OR_GPCM_ACS_DIV2 | \ 86 OR_GPCM_XACS | \ 87 OR_GPCM_SCY_2 | \ 88 OR_GPCM_TRLX_SET | \ 89 OR_GPCM_EHTR_SET | \ 90 OR_GPCM_EAD) 91 #else 92 /* 93 * Configuration for C2 on the local bus 94 */ 95 /* Window base at flash base */ 96 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE 97 /* Window size: 256 MB */ 98 #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 99 100 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ 101 BR_PS_8 | \ 102 BR_MS_GPCM | \ 103 BR_V) 104 105 #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE) | \ 106 OR_GPCM_CSNT | \ 107 OR_GPCM_ACS_DIV4 | \ 108 OR_GPCM_SCY_2 | \ 109 OR_GPCM_TRLX_SET | \ 110 OR_GPCM_EHTR_CLEAR | \ 111 OR_GPCM_EAD) 112 #endif 113 114 #if defined(CONFIG_TUXX1) 115 /* 116 * Configuration for C3 on the local bus 117 */ 118 /* Access window base at PINC3 base */ 119 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE 120 /* Window size: 256 MB */ 121 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 122 123 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ 124 BR_PS_8 | \ 125 BR_MS_GPCM | \ 126 BR_V) 127 128 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ 129 OR_GPCM_CSNT | \ 130 OR_GPCM_ACS_DIV2 | \ 131 OR_GPCM_SCY_2 | \ 132 OR_GPCM_TRLX_SET | \ 133 OR_GPCM_EHTR_CLEAR) 134 135 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 136 0x0000c000 | \ 137 MxMR_WLFx_2X) 138 #endif 139 140 #if defined(CONFIG_KMOPTI2) || defined(CONFIG_KMTEPR2) 141 /* 142 * Configuration for C3 on the local bus 143 */ 144 #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE 145 #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) 146 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ 147 BR_PS_16 | \ 148 BR_MS_GPCM | \ 149 BR_V) 150 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ 151 OR_GPCM_SCY_4 | \ 152 OR_GPCM_TRLX_CLEAR | \ 153 OR_GPCM_EHTR_CLEAR) 154 #endif 155 156 /* 157 * MMU Setup 158 */ 159 /* APP1: icache cacheable, but dcache-inhibit and guarded */ 160 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ 161 BATL_PP_RW | \ 162 BATL_MEMCOHERENCE) 163 /* 512M should also include APP2... */ 164 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ 165 BATU_BL_256M | \ 166 BATU_VS | \ 167 BATU_VP) 168 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ 169 BATL_PP_RW | \ 170 BATL_CACHEINHIBIT | \ 171 BATL_GUARDEDSTORAGE) 172 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 173 174 #if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5) 175 #define CONFIG_SYS_IBAT6L (0) 176 #define CONFIG_SYS_IBAT6U (0) 177 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L 178 #else 179 /* APP2: icache cacheable, but dcache-inhibit and guarded */ 180 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ 181 BATL_PP_RW | \ 182 BATL_MEMCOHERENCE) 183 #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ 184 BATU_BL_256M | \ 185 BATU_VS | \ 186 BATU_VP) 187 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ 188 BATL_PP_RW | \ 189 BATL_CACHEINHIBIT | \ 190 BATL_GUARDEDSTORAGE) 191 #endif 192 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 193 194 #define CONFIG_SYS_IBAT7L (0) 195 #define CONFIG_SYS_IBAT7U (0) 196 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 197 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 198 199 #endif /* __CONFIG_H */ 200